公开(公告)号：US06974653B2

公开(公告)日：2005-12-13

申请号：US10310640

申请日：2002-12-04

申请人： Frank C. Leung ,  Etsuya Morita ,  Christopher Howard Putnam ,  Holly H. Magoon ,  Ronald A. Pierce ,  Norman E. Roberts

发明人： Frank C. Leung ,  Etsuya Morita ,  Christopher Howard Putnam ,  Holly H. Magoon ,  Ronald A. Pierce ,  Norman E. Roberts

IPC分类号： G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70625 ,  G03F7/70641 ,  G03F7/70683

摘要： Methods for using critical dimension test marks (test marks) for the rapid determination of the best focus position of lithographic processing equipment and critical dimension measurement analysis across a wafer's surface are described. In a first embodiment, a plurality of test mark arrays are distributed across the surface of a wafer, a different plurality being created at a plurality of focus positions. Measurement of the length or area of the resultant test marks allows for the determination of the best focus position of the processing equipment. Critical dimension measurements at multiple points on a wafer with test marks allow for the determination of process accuracy and repeatability and further allows for the real-time detection of process degradation. Using test marks which require only a relatively simple optical scanner and sensor to measure their length or area, it is possible to measure hundreds of measurement values across a wafer in thirty minutes. Comparable measurements with a Scanning Electron Microscope (SEM) require at least five hours.

摘要翻译： 描述了使用关键维度测试标记（测试标记）快速确定光刻加工设备的最佳聚焦位置和晶片表面的临界尺寸测量分析的方法。 在第一实施例中，多个测试标记阵列分布在晶片的表面上，在多个焦点位置处形成不同的多个测试标记阵列。 所得测试标记的长度或面积的测量允许确定加工设备的最佳对焦位置。 具有测试标记的晶圆上的多个点的临界尺寸测量可以确定工艺精度和重复性，并进一步允许对工艺退化的实时检测。 使用仅需要相对简单的光学扫描仪和传感器测量其长度或面积的测试标记，可以在30分钟内测量跨越晶片的数百个测量值。 用扫描电子显微镜（SEM）进行的比较测量需要至少5个小时。

公开(公告)号：US5835227A

公开(公告)日：1998-11-10

申请号：US818375

申请日：1997-03-14

申请人： Ilya Grodnensky ,  Etsuya Morita ,  Kyoichi Suwa ,  Shigeru Hirukawa

发明人： Ilya Grodnensky ,  Etsuya Morita ,  Kyoichi Suwa ,  Shigeru Hirukawa

IPC分类号： G01M11/00 ,  G03F7/20 ,  G01B11/00 ,  G01B11/02

CPC分类号： G03F7/70058 ,  G03F7/70241 ,  G03F7/706

摘要： A method and apparatus for determining performance characteristics in lithographic tools includes projecting a predetermined image with a projection system having a known predetermined performance characteristic to obtain data indicative of the relationship between the size of the projected image and the predetermined performance characteristic. The same image is then projected in a system having an unknown value for the predetermined performance characteristic. The predetermined performance characteristic for the system under consideration is then determined based on the data obtained when the image was projected in the system having the known predetermined performance characteristic.

摘要翻译： 用于确定光刻工具中的性能特征的方法和装置包括用具有已知预定性能特征的投影系统投影预定图像，以获得指示投影图像的尺寸与预定性能特征之间的关系的数据。 然后将相同的图像投影在具有用于预定性能特征的未知值的系统中。 然后，基于在具有已知的预定性能特征的系统中投影图像时获得的数据来确定所考虑的系统的预定性能特性。

公开(公告)号：US07523429B2

公开(公告)日：2009-04-21

申请号：US11060927

申请日：2005-02-18

申请人： Armen Kroyan ,  Youping Zhang ,  Etsuya Morita ,  Adrianus Ligtenberg

发明人： Armen Kroyan ,  Youping Zhang ,  Etsuya Morita ,  Adrianus Ligtenberg

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.

摘要翻译： 公开了用于集成电路设计的系统和方法，以通过生成捕获局部布局要求的分级设计规则来提高电路布局的可制造性。 与采用全球设计规则的常规技术相比，本文所公开的IC设计系统和方法基于指定的布局和集成电路特性将原始设计布局分割成所需的粒度级别。 在本地化的层面上，适当地调整设计规则以从可制造性的角度捕获关键方面。 然后将这些调整后的设计规则用于执行本地化的布局操作和掩码数据转换。

公开(公告)号：US20050188338A1

公开(公告)日：2005-08-25

申请号：US11060927

申请日：2005-02-18

申请人： Armen Kroyan ,  Youping Zhang ,  Etsuya Morita ,  Adrianus Ligtenberg

发明人： Armen Kroyan ,  Youping Zhang ,  Etsuya Morita ,  Adrianus Ligtenberg

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.

摘要翻译： 公开了用于集成电路设计的系统和方法，以通过生成捕获局部布局要求的分级设计规则来提高电路布局的可制造性。 与采用全球设计规则的常规技术相比，本文所公开的IC设计系统和方法基于指定的布局和集成电路特性将原始设计布局分割成所需的粒度级别。 在本地化的层面上，适当地调整设计规则以从可制造性的角度捕获关键方面。 然后将这些调整后的设计规则用于执行本地化的布局操作和掩码数据转换。