公开(公告)号：US08168492B2

公开(公告)日：2012-05-01

申请号：US12754128

申请日：2010-04-05

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

IPC分类号： H01L21/8238

CPC分类号： H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66621

摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

摘要翻译： 在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。 在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。 以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

公开(公告)号：US08129777B2

公开(公告)日：2012-03-06

申请号：US12659008

申请日：2010-02-23

申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  In-Hyuk Choi

发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  In-Hyuk Choi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

摘要： In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.

摘要翻译： 在制造半导体器件的方法中，在衬底上形成有源沟道图案。 有源沟道图案包括彼此交替堆叠的初步栅极图案和单晶硅图案。 源极/漏极层形成在有源沟道图案的侧壁上。 在有源沟道图案和源极/漏极层上形成包括栅极沟槽的掩模图案结构。 选择性地蚀刻图案以形成隧道。 然后用栅电极填充栅极沟槽。 栅电极围绕有源沟道图案。 栅电极从有源沟道图案突出。 然后去除掩模图案结构。 将杂质注入源/漏区以形成源/漏区。 在源极/漏极区域上进行硅化处理以形成金属硅化物层，从而完成具有MOS晶体管的半导体器件。

公开(公告)号：US20110230001A1

公开(公告)日：2011-09-22

申请号：US13116374

申请日：2011-05-26

申请人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

发明人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

IPC分类号： H01L21/00

CPC分类号： H01L27/10 ,  G11C11/50 ,  H01L27/115

摘要： A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.

摘要翻译： 多位机电存储器件包括衬底，衬底上的位线，位线上的第一层间绝缘膜，第一层间绝缘膜上的第一和第二下字线，第一和第二下字线水平分开 通过沟槽彼此相邻的间隔件，邻接第一和第二下部字线中的每一个的侧壁的间隔件，接触孔内的焊盘电极，悬挂在第一和第二下部空隙中的第一和第二悬臂电极，其对应于 第一和第二下部字线设置在焊盘电极的两侧，第一和第二悬臂电极通过沟槽彼此分离，并且在垂直于第一和第二方向的第三方向上弯曲; 在所述焊盘电极上的第二层间绝缘膜，由所述第二层间绝缘膜支撑的第一和第二陷阱位置，以在所述第一和第二悬臂电极上具有第一和第二上部空隙，以及在所述第一和第二阱上的第一和第二上部字线 网站。

公开(公告)号：US20110189829A1

公开(公告)日：2011-08-04

申请号：US13084778

申请日：2011-04-12

申请人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Kyoung-Hwan Yeo

发明人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Kyoung-Hwan Yeo

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7926

摘要： A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.

摘要翻译： 存储器件包括衬底上的第一有源区和衬底上的第一和第二源极/漏极区，邻接第一有源区的相应的第一和第二侧壁。 第一栅极结构设置在第一和第二源/漏区之间的第一有源区上。 第二有源区域设置在第一栅极结构之间并邻接第一和第二源极/漏极区域。 第二栅极结构设置在覆盖第一栅极结构的第二有源区上。

公开(公告)号：US07973343B2

公开(公告)日：2011-07-05

申请号：US12154473

申请日：2008-05-23

申请人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

发明人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

IPC分类号： H01L29/66 ,  H01L29/84 ,  H01L21/00

CPC分类号： H01L27/10 ,  G11C11/50 ,  H01L27/115

摘要： A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.

摘要翻译： 多位机电存储器件包括衬底，衬底上的位线，位线上的第一层间绝缘膜，第一层间绝缘膜上的第一和第二下字线，第一和第二下字线水平分开 通过沟槽彼此相邻的间隔件，邻接第一和第二下部字线中的每一个的侧壁的间隔件，接触孔内的焊盘电极，悬挂在第一和第二下部空隙中的第一和第二悬臂电极，其对应于 第一和第二下部字线设置在焊盘电极的两侧，第一和第二悬臂电极通过沟槽彼此分离，并且在垂直于第一和第二方向的第三方向上弯曲; 在所述焊盘电极上的第二层间绝缘膜，由所述第二层间绝缘膜支撑的第一和第二陷阱位置，以在所述第一和第二悬臂电极上具有第一和第二上部空隙，以及在所述第一和第二阱上的第一和第二上部字线 网站。

公开(公告)号：US07911011B2

公开(公告)日：2011-03-22

申请号：US12693783

申请日：2010-01-26

申请人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim

发明人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim

IPC分类号： H01L29/84

CPC分类号： H01L27/10 ,  G11C23/00

摘要： Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided.

摘要翻译： 提供了包括具有包括绝缘特性的上表面的半导体衬底的机电非易失性存储器件。 第一电极图案设置在半导体衬底上。 第一电极图案暴露半导体衬底的表面的部分通过其中。 在第一电极图案和半导体衬底的暴露表面上提供保形位线。 位线与第一电极图案的侧壁间隔开，并且包括具有由电压差产生的弹性的导电材料。 绝缘层图案设置在位于半导体衬底上的位线的上表面上。 第二电极图案与位线间隔开并设置在绝缘层图案上。 第二电极图案面向第一电极图案。 还提供了相关方法。

公开(公告)号：US07790494B2

公开(公告)日：2010-09-07

申请号：US12007819

申请日：2008-01-16

申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

IPC分类号： H01L21/00 ,  H01L35/24 ,  H01L51/00 ,  H01L29/792

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673

摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

摘要翻译： 存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。 位线可以在第一方向上形成在基板上。 第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。 焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。 第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。 第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

公开(公告)号：US07719068B2

公开(公告)日：2010-05-18

申请号：US12002668

申请日：2007-12-18

申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

IPC分类号： G11C11/50

CPC分类号： H01L29/788 ,  G11C11/56 ,  G11C23/00

摘要： There are provided a multi-bit electro-mechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electro-mechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.

摘要翻译： 提供了能够增强或最大化存储器件的集成度的多位机电存储器件和制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线 并且沿第一方向延伸; 位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。 所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触 字线，并且在第二状态下与字线间隔开。

公开(公告)号：US07675142B2

公开(公告)日：2010-03-09

申请号：US11876111

申请日：2007-10-22

申请人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim

发明人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim

IPC分类号： H01L29/84

CPC分类号： H01L27/10 ,  G11C23/00

摘要： Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern.

摘要翻译： 提供了包括具有包括绝缘特性的上表面的半导体衬底的机电非易失性存储器件。 第一电极图案设置在半导体衬底上。 第一电极图案暴露半导体衬底的表面的部分通过其中。 在第一电极图案和半导体衬底的暴露表面上提供保形位线。 位线与第一电极图案的侧壁间隔开，并且包括具有由电压差产生的弹性的导电材料。 绝缘层图案设置在位于半导体衬底上的位线的上表面上。 第二电极图案与位线间隔开并设置在绝缘层图案上。 第二电极图案面向第一电极图案。

公开(公告)号：US20090239346A1

公开(公告)日：2009-09-24

申请号：US12477348

申请日：2009-06-03

申请人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided.

摘要翻译： FinFET半导体器件具有由半导体衬底形成并从衬底的表面突出的有源区。 具有第一突起和由有源区组成的第二突起的翅片平行布置在形成在有源区的中心部分的中心沟槽的每一侧。 第一突起和第二突起的上表面和侧表面包括通道区域。 通道离子注入层设置在中央沟槽的底部和鳍片的下部。 在鳍片上设置栅极氧化层。 栅电极设置在栅氧化层上。 源极区域和漏极区域设置在栅电极侧的有源区域中。 还提供了一种形成这种装置的方法。