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    System and Method for Automatic Instrument Address Recognition
    2.
    发明申请
    System and Method for Automatic Instrument Address Recognition 审中-公开
    自动仪器地址识别的系统和方法

    公开(公告)号：US20100050104A1

    公开(公告)日：2010-02-25

    申请号：US12195252

    申请日：2008-08-20

    申请人： Franco Stellari

    发明人： Franco Stellari

    IPC分类号： G06F13/20 ,  G06F3/048

    CPC分类号： G06F9/4411 ,  G06F13/385 ,  G06F2213/0052

    摘要： A method for automatic instrument address recognition includes requesting a list of instruments attached to a bus, collecting the list of instruments, querying each listed instrument for an identification string, comparing the identification string of each instrument to a matching pattern, and determining a match of the identification string with an instrument of interest, and selecting an address of the instrument having the identification string matching the matching pattern and returning the address for controlling the instrument of interest.

    摘要翻译： 一种用于自动仪器地址识别的方法包括：请求附接到总线的仪器的列表，收集仪器列表，查询每个列出的仪器的识别串，将每个仪器的识别串与匹配模式进行比较，以及确定 所述识别字符串与感兴趣的工具相关，并且选择具有与匹配模式匹配的识别字符串的仪器的地址，并返回用于控制感兴趣的仪器的地址。

    Optical trigger for PICA technique
    4.
    发明申请
    Optical trigger for PICA technique 失效
    PICA技术的光触发器

    公开(公告)号：US20060220664A1

    公开(公告)日：2006-10-05

    申请号：US11098850

    申请日：2005-04-05

    申请人： Franco Stellari ,  Peilin Song

    发明人： Franco Stellari ,  Peilin Song

    IPC分类号： G01R31/302

    CPC分类号： G01R31/31709 ,  G01R31/311

    摘要： Optical triggering system and method for synchronizing a test of an integrated circuit chip with its operation. An optical triggering system includes a testing mechanism, such as a PICA testing mechanism, for testing an integrated circuit chip. An optical trigger mechanism generates an optical trigger signal for synchronizing a test of the integrated circuit chip with its operation. The optical trigger mechanism provides an optical trigger signal having reduced jitter and a higher frequency rate than an electrical trigger signal resulting in a more accurate test of the integrated circuit chip.

    摘要翻译： 用于使集成电路芯片的测试与其操作同步的光触发系统和方法。 光触发系统包括用于测试集成电路芯片的诸如PICA测试机构的测试机构。 光学触发机构产生用于使集成电路芯片的测试与其操作同步的光学触发信号。 光学触发机构提供具有比电触发信号更少的抖动和更高频率的光学触发信号，导致集成电路芯片的更准确的测试。

    Navigating Analytical Tools Using Layout Software
    7.
    发明申请
    Navigating Analytical Tools Using Layout Software 有权
    使用布局软件导航分析工具

    公开(公告)号：US20110185325A1

    公开(公告)日：2011-07-28

    申请号：US12692198

    申请日：2010-01-22

    申请人： Franco Stellari ,  Peilin Song

    发明人： Franco Stellari ,  Peilin Song

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5022 ,  G06F17/5036

    摘要： A background process is used to install at least one system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and, responsive to the call message, current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software, based on the representation of the current layout coordinates. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Responsive to the call message, current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout, corresponding to the representation of the current coordinates from the tool control software, is displayed.

    摘要翻译： 后台进程用于安装至少一个系统挂钩，用于消息拦截集成电路芯片布局显示软件。 通过系统挂钩拦截呼叫消息，并响应于呼叫消息，从集成电路芯片布局显示软件读取当前布局坐标。 将当前布局坐标的表示输入到被配置为控制用于分析集成电路的物理工具的工具控制软件中，并且基于当前布局坐标的表示，通过工具控制软件来控制物理工具。 在“反向”方法中，使用后台进程来安装至少一个用于消息拦截的系统钩子，用于控制用于分析集成电路的物理工具的工具控制软件，并且通过系统钩子拦截呼叫消息。 响应于通话消息，从工具控制软件读取当前坐标。 将当前坐标的表示输入到集成电路芯片布局显示软件中，并且显示对应于来自刀具控制软件的当前坐标的表示的集成电路布局的至少一部分。

    Process variation on-chip sensor
    8.
    发明授权
    Process variation on-chip sensor 失效
    过程变化片上传感器

    公开(公告)号：US07868606B2

    公开(公告)日：2011-01-11

    申请号：US12032100

    申请日：2008-02-15

    申请人： Mesut Meterelliyoz ,  Peilin Song ,  Franco Stellari

    发明人： Mesut Meterelliyoz ,  Peilin Song ,  Franco Stellari

    IPC分类号： G01N27/00

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Improved process variation sensors and techniques are disclosed, wherein both global and local variations associated with transistors on an integrated circuit can be monitored. For example, respective circuits for sensing a global process variation, a local process variation between neighboring negative-channel type transistors, and a local process variation between neighboring positive-channel type transistors are disclosed. Further, in one example, a method for sensing a process variation associated with transistors on an integrated circuit includes providing at least one process variation sensor on the integrated circuit, the process variation sensor comprising a sensing portion including one or more transistors and a loading and amplification portion including one or more transistors, and operating the one or more transistors of the sensing portion and the one or more transistors of the loading and amplification portion in a subthreshold region of transistor operation such that when a threshold voltage of at least one of the transistors changes, a process variation is sensed.

    摘要翻译： 公开了改进的工艺变化传感器和技术，其中可以监测与集成电路上的晶体管相关联的全局和局部变化。 例如，公开了用于感测全局处理变化的相应电路，相邻负信道型晶体管之间的局部处理变化以及相邻正通道型晶体管之间的局部工艺变化。 此外，在一个示例中，用于感测与集成电路上的晶体管相关联的工艺变化的方法包括在集成电路上提供至少一个工艺变化传感器，所述工艺变化传感器包括感测部分，其包括一个或多个晶体管， 放大部分包括一个或多个晶体管，并且在晶体管操作的亚阈值区域中操作感测部分的一个或多个晶体管和负载和放大部分的一个或多个晶体管，使得当晶体管操作中的至少一个的阈值电压 晶体管变化，感测到工艺变化。

    Measuring and predicting VLSI chip reliability and failure
    10.
    发明授权
    Measuring and predicting VLSI chip reliability and failure 失效
    测量和预测VLSI芯片的可靠性和故障

    公开(公告)号：US07480882B1

    公开(公告)日：2009-01-20

    申请号：US12049344

    申请日：2008-03-16

    申请人： Peilin Song ,  David Heidel ,  Franco Motika ,  Franco Stellari

    发明人： Peilin Song ,  David Heidel ,  Franco Motika ,  Franco Stellari

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G06F11/27 ,  G01R31/3187 ,  G01R31/28

    CPC分类号： G01R31/318536

    摘要： This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

    摘要翻译： 该实施例取代了LBIST的使用以获得通过或不通过结果。 选择性签名功能用于通过在一个周期时间内抖动芯片来收集顶部故障路径。 这些路径可以片上或片外存储，供以后使用。 一旦芯片在现场运行一段时间，执行相同的过程来收集最上面的故障路径，并将其与存储的旧路径进行比较。 如果顶部路径的顺序发生变化，则表示（例如）有一个路径（不是最慢的路径）比其他路径慢，这可能是潜在的可靠性问题。 因此，在现场确定潜在的可靠性故障。