公开(公告)号：US07043221B2

公开(公告)日：2006-05-09

申请号：US10486624

申请日：2002-07-19

申请人： Fabrice Jovenin ,  David Canard

发明人： Fabrice Jovenin ,  David Canard

IPC分类号： H04B1/10

CPC分类号： H03B21/02 ,  H03D7/18

摘要： A mixer circuit with image frequency rejection comprising a quadrature phase divider (30, 30′) presenting an input connected to the input (Fi) of the mixer circuit and two outputs respectively delivering two signals in phase quadrature which are applied respectively to two simple mixers (31, 32; 31′, 32′), said mixer circuit comprising a quadrature phase and frequency divider (33, 33′) having a frequency division ratio and presenting two inputs respectively connected to the respective outputs of the two simple mixers (31, 32; 31′, 32′) and a first output delivering a first output signal (Fo) of the mixer circuit, which signal is applied to the inputs of the two simple mixers.

摘要翻译： 一种具有图像频率抑制的混频器电路，包括正交相位分配器（30,30'），其呈现连接到混频器电路的输入端（F SUB）的输入端和两个输出端，分别传送相位正交的两个信号 它们分别应用于两个简单混合器（31,32; 31'，32'），所述混频器电路包括具有分频比的正交相位和分频器（33,33'），并且呈现分别连接到相应 两个简单混合器（31,32; 31'，32'）的输出和第一输出端输出混频器电路的第一输出信号（F SUB），该信号被施加到 两个简单的混音器。

公开(公告)号：US06597250B2

公开(公告)日：2003-07-22

申请号：US09965413

申请日：2001-09-27

申请人： Fabrice Jovenin

发明人： Fabrice Jovenin

IPC分类号： H03B100

CPC分类号： H03L7/1976 ,  H03L7/099 ,  H03L7/1978

摘要： A frequency synthesizer comprising a phase-locked loop that includes a phase-frequency comparator (16), at least a voltage-controlled oscillator (12) associated with a selection apparatus (50, 80, 82) of an oscillation frequency band, and a frequency divider (14) connected between the oscillator and the comparator. A voltage source proper (90) is connected to the selection apparatus for supplying it with a control voltage proper.

摘要翻译： 一种频率合成器，包括锁相环路，该锁相环路包括相位频率比较器（16），至少一个与振荡频带的选择装置（50,80,82）相关联的压控振荡器（12），以及 分频器（14）连接在振荡器和比较器之间。 电压源本体（90）连接到选择装置，为其提供适当的控制电压。

公开(公告)号：US06703901B2

公开(公告)日：2004-03-09

申请号：US09965455

申请日：2001-09-27

申请人： Fabrice Jovenin ,  Dominique Brunel ,  Zhizhong Wang

发明人： Fabrice Jovenin ,  Dominique Brunel ,  Zhizhong Wang

IPC分类号： H03L700

CPC分类号： H03L7/1978 ,  H03L7/099

摘要： A frequency synthesizer comprising a phase-locked loop (10) and comprising: a frequency divider (14) having integral dividing ratios, a sigma-delta modulator (30) connected to the frequency divider for obtaining a resulting mean dividing ratio having a fractional component, the modulator having an input for an adjusting instruction, and at least a frequency divider (100) having a fixed fractional dividing ratio, and means (120, 40) for activating the divider having a fractional dividing ratio when the fractional component (k) of the mean dividing ratio is contained in at least a given value range, and for modifying the adjusting instruction in corresponding manner.

摘要翻译： 一种频率合成器，包括锁相环（10），并包括：具有整数分频比的分频器（14），连接到分频器的Σ-Δ调制器（30），用于获得具有分数分量 ，调制器具有用于调整指令的输入，以及至少具有固定分数分频比的分频器（100），以及用于当所述调制指令的分数分量（k）为 平均分割比率至少包含给定值范围，并以相应的方式修改调整指令。

公开(公告)号：US06278871B1

公开(公告)日：2001-08-21

申请号：US09467593

申请日：1999-12-20

申请人： Fabrice Jovenin ,  Benoît Butaye

发明人： Fabrice Jovenin ,  Benoît Butaye

IPC分类号： H04B126

CPC分类号： H01L28/40 ,  H01L27/0676 ,  H01L27/0688 ,  H01L27/0808

摘要： The present invention relates to an integrated circuit comprising a series of conducting layers (1) . . . (6), separated in pairs by insulating layers, including a capacitive element CF formed by a stack of conducting layers cut out of the conducting layers. According to the invention, the capacitive element CF comprises as many conductive plates as the integrated circuit has conducting layers. The invention enables to maximize the reduction of the influence of each of its manufacturing steps on the real value of the capacitive element CF.

摘要翻译： 本发明涉及包括一系列导电层（1）的集成电路。 。 。 （6），由绝缘层成对分离，包括由从导电层切出的导电层堆叠形成的电容元件CF。根据本发明，电容元件CF包括与集成电路具有导电性的导电板一样多的导电板 本发明能够最大限度地减少其每个制造步骤对电容元件CF的实际值的影响。

公开(公告)号：US08552772B2

公开(公告)日：2013-10-08

申请号：US12985566

申请日：2011-01-06

申请人： Fabrice Jovenin

发明人： Fabrice Jovenin

IPC分类号： H03L7/06

CPC分类号： H03L7/093 ,  H03L7/18

摘要： A system in accordance with the present invention may include a phase-locked loop circuit, comprising a first input signal oscillating at a reference frequency, a second input signal received from a voltage-controlled oscillator (VCO) after passing through an N-divider, a phase detector and charge-pump, the phase detector comparing a phase of the first input signal and a phase of the second input signal, a loop filter in series with the phase detector and charge-pump, the loop filter having an integrator, a pole zero, and a post-filter, and a buffer in parallel with the integrator and in series with the post-filter, the buffer receiving an output signal from the integrator and isolating the integrator from an input impedance of the post-filter, and the buffer having a multiplexer for selecting between a plus and minus level shift signal, wherein the VCO is in series with the loop filter and the N-divider, and the VCO is configured to receive a tuning voltage signal from the loop filter.

摘要翻译： 根据本发明的系统可以包括锁相环电路，其包括以参考频率振荡的第一输入信号，在经过N分频器之后从压控振荡器（VCO）接收的第二输入信号， 相位检测器和电荷泵，相位检测器将第一输入信号的相位和第二输入信号的相位进行比较，与相位检测器和电荷泵串联的环路滤波器，环路滤波器具有积分器， 后置滤波器和与积分器并联并与后置滤波器串联的缓冲器，缓冲器接收来自积分器的输出信号，并将积分器与后置滤波器的输入阻抗隔离，以及 所述缓冲器具有用于在正电平和负电平移位信号之间进行选择的多路复用器，其中所述VCO与所述环路滤波器和所述N分频器串联，并且所述VCO被配置为从所述环路滤波器接收调谐电压信号 。

公开(公告)号：US20120176171A1

公开(公告)日：2012-07-12

申请号：US12985566

申请日：2011-01-06

申请人： Fabrice JOVENIN

发明人： Fabrice JOVENIN

IPC分类号： H03L7/08

CPC分类号： H03L7/093 ,  H03L7/18

摘要： A system in accordance with the present invention may include a phase-locked loop circuit, comprising a first input signal oscillating at a reference frequency, a second input signal received from a voltage-controlled oscillator (VCO) after passing through an N-divider, a phase detector and charge-pump, the phase detector comparing a phase of the first input signal and a phase of the second input signal, a loop filter in series with the phase detector and charge-pump, the loop filter having an integrator, a pole zero, and a post-filter, and a buffer in parallel with the integrator and in series with the post-filter, the buffer receiving an output signal from the integrator and isolating the integrator from an input impedance of the post-filter, and the buffer having a multiplexer for selecting between a plus and minus level shift signal, wherein the VCO is in series with the loop filter and the N-divider, and the VCO is configured to receive a tuning voltage signal from the loop filter.

摘要翻译： 根据本发明的系统可以包括锁相环电路，其包括以参考频率振荡的第一输入信号，在经过N分频器之后从压控振荡器（VCO）接收的第二输入信号， 相位检测器和电荷泵，相位检测器将第一输入信号的相位和第二输入信号的相位进行比较，与相位检测器和电荷泵串联的环路滤波器，环路滤波器具有积分器， 后置滤波器和与积分器并联并与后置滤波器串联的缓冲器，缓冲器接收来自积分器的输出信号，并将积分器与后置滤波器的输入阻抗隔离，以及 所述缓冲器具有用于在正电平和负电平移位信号之间进行选择的多路复用器，其中所述VCO与所述环路滤波器和所述N分频器串联，并且所述VCO被配置为从所述环路滤波器接收调谐电压信号 。

公开(公告)号：US06661291B2

公开(公告)日：2003-12-09

申请号：US09965412

申请日：2001-09-27

申请人： Fabrice Jovenin

发明人： Fabrice Jovenin

IPC分类号： H03L700

CPC分类号： H03L7/1974 ,  H03J5/00 ,  H03J5/0245 ,  H03J5/24 ,  H03J7/065 ,  H03J2200/10 ,  H03J2200/29 ,  H03L7/099 ,  H03L2207/06

摘要： The present invention relates a frequency synthesizer comprising in a phase-locked loop: a phase-frequency comparator (16) connected to a reference frequency source (20), at least a voltage-controlled oscillator (12) and a fractional frequency divider (14) suitable for producing a mean dividing ratio having an integral component and a fractional component. According to the invention, the oscillator comprises a plurality of oscillator stages which have different center frequencies, and the synthesizer further includes means for selecting an oscillator stage as a function of the integral component of the mean dividing ratio. Application to portable telephones.

摘要翻译： 本发明涉及一种频率合成器，包括：锁相环：连接到参考频率源（20）的至少一个压控振荡器（12）和一个分数分频器（14）的相位 - 频率比较器（16） 适合于产生具有积分分量和分数分量的平均分频比。根据本发明，振荡器包括具有不同中心频率的多个振荡器级，并且合成器还包括用于选择振荡器级作为 平均分频比的积分分量。应用于便携式电话。

公开(公告)号：US06529720B1

公开(公告)日：2003-03-04

申请号：US09467597

申请日：1999-12-20

申请人： Fabrice Jovenin ,  Sever Cercelaru

发明人： Fabrice Jovenin ,  Sever Cercelaru

IPC分类号： H04B126

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L27/0688 ,  H01L27/08

摘要： An integrated circuit includes at least an inductive element and an active region which may include resistive, capacitive and semiconductor elements. The inductive element and part of the active region are superimposed. The integrated circuit has a screen for insulating the active region with respect to an electromagnetic field that the inductive element develops. The screen allows the implementation of inductive elements having high quality factors in integrated circuits of reduced size and in which the electromagnetic interactions between the inductive elements and the other elements are reduced.

摘要翻译： 集成电路至少包括电感元件和有源区域，其可以包括电阻，电容和半导体元件。 电感元件和有源区域的一部分被叠加。 集成电路具有用于使有源区域相对于感应元件形成的电磁场绝缘的屏幕。 该屏幕允许在减小尺寸的集成电路中实现具有高质量因素的电感元件，并且其中电感元件和其它元件之间的电磁相互作用减小。

公开(公告)号：US5937340A

公开(公告)日：1999-08-10

申请号：US946483

申请日：1997-10-07

申请人： Pascal Philippe ,  Mihai Murgulescu ,  Fabrice Jovenin

发明人： Pascal Philippe ,  Mihai Murgulescu ,  Fabrice Jovenin

IPC分类号： H03K3/282 ,  H03B1/00 ,  H03B1/04 ,  H03B5/12 ,  H04B1/40 ,  H04B1/10

CPC分类号： H03B5/1231 ,  H03B5/1215 ,  H03B5/1243 ,  H03B2200/0032 ,  H03B2200/004 ,  H03B2200/0088 ,  H03B2200/0098 ,  H03B2201/0208 ,  H03B2202/042 ,  H03B2202/05

摘要： The invention relates to an oscillator OSC intended to provide an output signal having a frequency which is variable as a function of a tuning voltage Vtun. The oscillator OSC includes a passive part having two series-arranged variable capacitances Cs, biased by the tuning voltage Vtun, and connected to a power supply VCC via two inductances Lext, and an active part having a first transistor T1 and a second transistor T2 whose collectors are connected to the output terminals C1 and C2 of the passive part, the base of one transistor being connected to the collector of the other transistor via a coupling capacitor Cfb. According to the invention, the passive part includes two high-pass filters, each being inserted between one of the output terminals S1 or S2 and one of the variable capacitances Cs, which allows a reduction of the active part's sensitivity to low-frequency noise.

摘要翻译： 本发明涉及一种旨在提供具有作为调谐电压Vtun的函数可变的频率的输出信号的振荡器OSC。 振荡器OSC包括具有由调谐电压Vtun偏置的两个串联布置的可变电容Cs的无源部分，并且经由两个电感Lext连接到电源VCC，以及具有第一晶体管T1和第二晶体管T2的有源部分 集电极连接到无源部分的输出端子C1和C2，一个晶体管的基极通过耦合电容器Cfb连接到另一晶体管的集电极。 根据本发明，无源部分包括两个高通滤波器，每个高通滤波器插入在一个输出端子S1或S2和一个可变电容Cs之间，这允许有源部分对低频噪声的灵敏度降低。