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    Interlaced memory device with random or sequential access
    2.
    发明授权
    Interlaced memory device with random or sequential access 有权
    具有随机或顺序访问的隔行存储器件

    公开(公告)号：US06701419B2

    公开(公告)日：2004-03-02

    申请号：US09977561

    申请日：2001-10-15

    申请人： Francesco Tomaiuolo ,  Salvatore Nicosia ,  Luigi Pascucci

    发明人： Francesco Tomaiuolo ,  Salvatore Nicosia ,  Luigi Pascucci

    IPC分类号： G06F1200

    CPC分类号： G11C7/1033 ,  G11C7/1045

    摘要： A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

    摘要翻译： 多用途隔行存储器件具有两种不同的同步和异步模式。 存储器使用用于检测地址转换的电路，用作系统的同步时钟，以通过使当前输入的外部地址与存储在地址计数器中的当前输入的外部地址进行比较来使存储器件的控制电路识别所需的访问模式 的两行记忆体。 存储装置包括用于输出数据的缓冲器。 缓冲器包括用于将输出节点预充电到对应于两个可能逻辑状态的电压之间的中间电压的电路，从而降低噪声并改善传输时间。

    Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data
    3.
    发明授权
    Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data 有权
    用于交错存储器和负载脉冲发生器电路的交错数据路径和输出管理架构，用于输出读取的数据

    公开(公告)号：US06470431B2

    公开(公告)日：2002-10-22

    申请号：US09774542

    申请日：2001-01-31

    申请人： Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

    发明人： Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

    IPC分类号： C06F1200

    CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    摘要： An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

    摘要翻译： 具有交错数据路径的交错存储器包括分成第一存储单元组和第二存储单元组的存储器单元的阵列，分别耦合到第一和第二存储单元组的读出放大器的第一和第二阵列，以及 分别耦合到第一和第二读出放大器阵列的第一和第二读取寄存器。 控制和定时电路连接到第一和第二读出放大器阵列，并且具有用于接收外部产生的命令信号的输入，以及用于提供路径选择信号和控制信号的输出。 第三寄存器连接到第一和第二读取寄存器，并且具有用于根据路径选择信号接收其中的读取数据的输入。 一个通道阵列连接到第三寄存器，并被控制信号共同控制，以便将存储在第三寄存器中的读取数据传送到输出缓冲器阵列。

    Circuit for controlling a reference node in a sense amplifier
    4.
    发明授权
    Circuit for controlling a reference node in a sense amplifier 有权
    用于控制读出放大器中的参考节点的电路

    公开(公告)号：US06801466B2

    公开(公告)日：2004-10-05

    申请号：US10331147

    申请日：2002-12-27

    申请人： Salvatore Giove ,  Luca De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiulo ,  Kumar Promod ,  Giuseppe Piazza ,  Francesco Pipitone

    发明人： Salvatore Giove ,  Luca De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiulo ,  Kumar Promod ,  Giuseppe Piazza ,  Francesco Pipitone

    IPC分类号： G11C702

    CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C16/28

    摘要： A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.

    摘要翻译： 提供了一种用于控制在操作模式和待机模式之间切换的读出放大器中的参考节点的电路。 参考节点在工作模式下提供参考电压。 电路可以包括用于在进入待机模式时使参考节点进入起始电压的电路，用于将参考节点保持在备用模式下的预充电电压的电路，以及用于提供比较电压更接近的电路 到预充电电压比启动电压。 还可以包括牵引电路以将参考节点拉向电源电压。 此外，控制器可以在进入待机模式时激活拉电路，并且当参考节点处的电压达到比较电压时禁止拉电路。

    Circuit for managing the transfer of data streams from a plurality of sources within a system
    5.
    发明授权
    Circuit for managing the transfer of data streams from a plurality of sources within a system 有权
    用于管理从系统内的多个源传输数据流的电路

    公开(公告)号：US06487140B2

    公开(公告)日：2002-11-26

    申请号：US09773363

    申请日：2001-01-31

    申请人： Francesco Tomaiuolo ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

    发明人： Francesco Tomaiuolo ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

    IPC分类号： G11C800

    CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    摘要： A control circuit manages transferring of data within a system, such as an interleaved memory. The system includes a plurality of data sources for providing an output data stream synchronous with an external timing signal, an output register for storing data available at an output of the system, and a selection multiplexer for transferring the data from the plurality of data sources to the output register. The control circuit includes a plurality of circuit blocks, with each circuit block being dedicated to one of the plurality of data sources. Each circuit block includes a detection circuit for detecting availability of the data at an output of a selected data source, and a conditioned update path connected to the detection circuit provides an update flag. A logic gate having a first input receives the update flag and a second input receives an output signal from the detection circuit for providing a selection signal for the selection multiplexer.

    摘要翻译： 控制电路管理诸如交错存储器之类的系统内的数据的传送。 该系统包括用于提供与外部定时信号同步的输出数据流的多个数据源，用于存储在系统的输出端可用的数据的输出寄存器，以及用于将数据从多个数据源传送到 输出寄存器。 控制电路包括多个电路块，每个电路块专用于多个数据源之一。 每个电路块包括检测电路，用于检测所选择的数据源的输出端的数据的可用性，并且连接到检测电路的条件更新路径提供更新标志。 具有第一输入的逻辑门接收更新标志，第二输入接收来自检测电路的输出信号，为选择多路复用器提供选择信号。

    Pre-charging circuit of an output buffer
    6.
    发明授权
    Pre-charging circuit of an output buffer 有权
    输出缓冲器的预充电电路

    公开(公告)号：US06469566B2

    公开(公告)日：2002-10-22

    申请号：US09773268

    申请日：2001-01-31

    申请人： Salvatore Nicosia

    发明人： Salvatore Nicosia

    IPC分类号： H03K1704

    CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    摘要： A pre-charging circuit for the output node of an output buffer of an integrated digital system generates a first pulse for enabling the output of new data and a second pulse having a shorter duration than the first pulse for loading the new data in an output data register. The output data register is coupled to the input of the output buffer. A capacitor is connected in parallel to the load capacitance of the output node of the buffer by a pass-gate. The pass-gate is enabled by a pre-charge command corresponding to the logic AND of the second pulse and of the logic XOR of the new data and the data currently present on the output node. A driver is disabled by the first pulse for charging the capacitor to a voltage corresponding to the logic level of data belonging to the group that includes the new data and a logic inversion of the current data.

    摘要翻译： 用于集成数字系统的输出缓冲器的输出节点的预充电电路产生用于使新数据的输出的第一脉冲和具有比第一脉冲更短的持续时间的第二脉冲，用于将新数据加载到输出数据中 寄存器。 输出数据寄存器耦合到输出缓冲器的输入端。 电容器通过闸门与缓冲器的输出节点的负载电容并联连接。 通过对应于第二脉冲的逻辑AND和新数据的逻辑和和输出节点上当前存在的数据的预充电命令来使能通过门。 通过用于将电容器充电到与属于包括新数据的组的数据的逻辑电平相对应的电压和当前数据的逻辑反相的第一脉冲禁用驱动器。

    Accelerated carry generation
    8.
    发明授权
    Accelerated carry generation 有权
    加速进位产生

    公开(公告)号：US06366634B2

    公开(公告)日：2002-04-02

    申请号：US09774878

    申请日：2001-01-31

    申请人： Luca Giuseppe De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Promod Kumar ,  Carmelo Condemi

    发明人： Luca Giuseppe De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Promod Kumar ,  Carmelo Condemi

    IPC分类号： G06M300

    CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    摘要： An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.

    摘要翻译： 用于交织的地址二进制计数器，其具有被划分为第一存储单元组和第二存储单元组的存储器单元的阵列，包括与存储在一行存储单元 银行和进位计算网络。 交织的存储器以启用信号启用的突发存取模式工作。 进位计算网络包括有序组的独立进位发生器。 每个独立进位发生器包括一定数量的级，其中每个级具有从最低有效位开始有序地接收其自身使能位和存储体的一行的连续位数等于级数的输入。 有序组的第一进位发生器的使能位是使能信号，有序组的任何其他进位发生器的使能位是使能信号和先前进位发生器的输入位的逻辑“与” 订购组。

    Data output buffer with precharge
    9.
    发明授权
    Data output buffer with precharge 有权
    预充电数据输出缓冲器

    公开(公告)号：US06292405B1

    公开(公告)日：2001-09-18

    申请号：US09636363

    申请日：2000-08-11

    申请人： Salvatore Nicosia ,  Giovanni Pagano ,  Luca Giuseppe De Ambroggi ,  Gaetano Palumbo

    发明人： Salvatore Nicosia ,  Giovanni Pagano ,  Luca Giuseppe De Ambroggi ,  Gaetano Palumbo

    IPC分类号： G11C700

    CPC分类号： G11C7/1057 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106

    摘要： A data output buffer includes an output node, and a first stage connected to the output node for providing a first control signal for precharging the output node to an intermediate voltage with respect to a voltage for switching the output node from a current logic state to a different logic state. A second stage is connected to the first stage and to the output buffer. The first and second stages are responsive to a second control signal for enabling output of new data. A precharge logic circuit precharges the output node to the intermediate voltage as a function of data last output, and as a function of first and second reset signals until a rising and falling edge of the data last output respectively crosses the intermediate voltage.

    摘要翻译： 数据输出缓冲器包括输出节点和连接到输出节点的第一级，用于提供用于将输出节点预充电到相对于将输出节点从当前逻辑状态切换到电压的电压的中间电压的第一控制信号 不同的逻辑状态。 第二级连接到第一级和输出缓冲器。 第一和第二阶段响应于第二控制信号以使得能够输出新的数据。 预充电逻辑电路根据数据最后输出将输出节点预充电到中间电压，并且作为第一和第二复位信号的函数，直到数据最后输出的上升沿和下降沿分别跨越中间电压。