公开(公告)号：US06810449B1

公开(公告)日：2004-10-26

申请号：US09480767

申请日：2000-01-10

申请人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

发明人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

IPC分类号： G06F300

CPC分类号： G06F13/161 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12

摘要： A system and method for performing data transfers within a computer system is provided The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

摘要翻译： 提供了一种用于在计算机系统内执行数据传输的系统和方法。该系统包括控制器，其被配置为动态地调整执行一系列数据传送操作所需的通信的交错，以最大限度地利用通信所在的信道 执行。 控制器能够通过用与控制信息分开发送的选通信号通过信令数据传送的开始来改变请求数据传送的控制信息的传输与数据传送的执行之间的时间间隔。 控制器能够通过启动具有终止信号的数据传送的终止来推迟在操作中传送多少数据的确定。 该方法提供了用于区分同一行上承载的相同控制信号的技术。 该系统包括具有控制电路的存储器件，该控制电路允许不超过一个由任何给定电源线供电的存储体进行感测或预充电操作。

公开(公告)号：US06542976B2

公开(公告)日：2003-04-01

申请号：US09583111

申请日：2000-05-23

申请人： Richard Maurice Barth ,  Mark Alan Horowitz ,  Craig Edward Hampel ,  Frederick Abbot Ware

发明人： Richard Maurice Barth ,  Mark Alan Horowitz ,  Craig Edward Hampel ,  Frederick Abbot Ware

IPC分类号： G06F1314

CPC分类号： G11C7/222 ,  G06F13/16 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  Y02D10/14

摘要： A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

摘要翻译： 提供了一种用于在计算机系统内传送信息的方法和系统。 该系统包括具有较低功率模式的存储器件，其中数据传输电路不由时钟信号驱动，并且其中数据传输电路由时钟信号驱动的较高功率模式。 该系统还包括存储器控制器，其向控制信号发送控制信号以发起数据传输交易。 存储器装置异步地接收控制信号，并且响应于一个控制信号而呈现第二模式。 当存储器件处于第二模式时，存储器控制器发送控制信号以识别特定的时钟周期。 存储设备同步传输数据。 存储器件基于所识别的时钟周期和指定的数据传输的类型确定何时开始数据传输。

公开(公告)号：US07085906B2

公开(公告)日：2006-08-01

申请号：US10288045

申请日：2002-11-05

申请人： Richard Maurice Barth ,  Mark Alan Horowitz ,  Craig Edward Hampel ,  Frederick Abbot Ware

发明人： Richard Maurice Barth ,  Mark Alan Horowitz ,  Craig Edward Hampel ,  Frederick Abbot Ware

IPC分类号： G06F13/14

CPC分类号： G11C7/222 ,  G06F13/16 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  Y02D10/14

摘要： A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

摘要翻译： 提供了一种用于在计算机系统内传送信息的方法和系统。 该系统包括具有较低功率模式的存储器件，其中数据传输电路不由时钟信号驱动，并且其中数据传输电路由时钟信号驱动的较高功率模式。 该系统还包括存储器控制器，其向控制信号发送控制信号以发起数据传输交易。 存储器装置异步地接收控制信号，并且响应于一个控制信号而呈现第二模式。 当存储器件处于第二模式时，存储器控制器发送控制信号以识别特定的时钟周期。 存储设备同步传输数据。 存储器件基于所识别的时钟周期和指定的数据传输的类型确定何时开始数据传输。

公开(公告)号：US06931467B2

公开(公告)日：2005-08-16

申请号：US10094547

申请日：2002-03-08

申请人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

发明人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/12 ,  G06F13/00

CPC分类号： G11C7/1078 ,  G06F13/161 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1072 ,  G11C7/109 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096

摘要： A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

摘要翻译： 提供了一种用于在计算机系统内执行数据传输的系统和方法。 该系统包括控制器，该控制器被配置为动态地调整执行一系列数据传送操作所需的通信的交错，以最大限度地利用要进行通信的信道的利用。 控制器能够通过用与控制信息分开发送的选通信号通过信令数据传送的开始来改变请求数据传送的控制信息的传输与数据传送的执行之间的时间间隔。 控制器能够通过启动具有终止信号的数据传送的终止来推迟在操作中传送多少数据的确定。 该方法提供了用于区分同一行上承载的相同控制信号的技术。 该系统包括具有控制电路的存储器件，该控制电路允许不超过一个由任何给定电源线供电的存储体进行感测或预充电操作。

公开(公告)号：US06532522B1

公开(公告)日：2003-03-11

申请号：US09718908

申请日：2000-11-21

申请人： Richard Maurice Barth ,  Mark Alan Horowitz ,  Craig Edward Hampel ,  Frederick Abbot Ware

发明人： Richard Maurice Barth ,  Mark Alan Horowitz ,  Craig Edward Hampel ,  Frederick Abbot Ware

IPC分类号： G06F1314

CPC分类号： G11C7/222 ,  G06F13/16 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  Y02D10/14

摘要： A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

公开(公告)号：US6122688A

公开(公告)日：2000-09-19

申请号：US979402

申请日：1997-11-26

申请人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

发明人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

IPC分类号： G06F12/00 ,  G06F13/16 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/12 ,  G11C11/401 ,  G06F13/00

CPC分类号： G11C7/22 ,  G06F13/161 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1072 ,  G11C8/12

摘要： A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

公开(公告)号：US07315929B2

公开(公告)日：2008-01-01

申请号：US11742344

申请日：2007-04-30

申请人： Richard Maurice Barth ,  Mark Alan Horowitz ,  Craig Edward Hampel ,  Frederick Abbot Ware

发明人： Richard Maurice Barth ,  Mark Alan Horowitz ,  Craig Edward Hampel ,  Frederick Abbot Ware

IPC分类号： G06F13/14

CPC分类号： G11C7/222 ,  G06F13/16 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  Y02D10/14

摘要： A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

摘要翻译： 提供了一种用于在计算机系统内传送信息的方法和系统。 该系统包括具有较低功率模式的存储器件，其中数据传输电路不由时钟信号驱动，并且其中数据传输电路由时钟信号驱动的较高功率模式。 该系统还包括存储器控制器，其向控制信号发送控制信号以发起数据传输交易。 存储器装置异步地接收控制信号，并且响应于一个控制信号而呈现第二模式。 当存储器件处于第二模式时，存储器控制器发送控制信号以识别特定的时钟周期。 存储设备同步传输数据。 存储器件基于所识别的时钟周期和指定的数据传输的类型确定何时开始数据传输。

公开(公告)号：US07287109B2

公开(公告)日：2007-10-23

申请号：US10966767

申请日：2004-10-15

申请人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

发明人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

IPC分类号： G06F13/00

CPC分类号： G11C7/1078 ,  G06F13/161 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1072 ,  G11C7/109 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096

摘要： Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sampling write data that is stored in the memory core during the write operation. A first bit of the write data is provided to the memory device during an even phase of a clock signal. A second bit of the write data is provided to the memory device during an odd phase of the clock signal.

摘要翻译： 提供了包括向存储器件提供控制信息的方法实施例。 控制信息包括指定在存储器件中启动写操作的第一代码。 提供了一个信号，指示在写入操作期间存储器件何时开始对存储在存储器核心中的写入数据进行采样。 在时钟信号的偶数阶段期间，写入数据的第一位被提供给存储器件。 在时钟信号的奇数阶段期间，写数据的第二位被提供给存储器件。

公开(公告)号：US06591353B1

公开(公告)日：2003-07-08

申请号：US09561868

申请日：2000-05-01

申请人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

发明人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

IPC分类号： G06F1200

CPC分类号： G06F13/161 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12

摘要： A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

公开(公告)号：US06470405B2

公开(公告)日：2002-10-22

申请号：US09870322

申请日：2001-05-29

申请人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

发明人： Richard Maurice Barth ,  Frederick Abbot Ware ,  John Bradly Dillon ,  Donald Charles Stark ,  Craig Edward Hampel ,  Matthew Murdy Griffin

IPC分类号： G06F1300

CPC分类号： G11C7/1078 ,  G06F13/161 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1072 ,  G11C7/109 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096

摘要： A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

摘要翻译： 提供了一种用于在计算机系统内执行数据传输的系统和方法。 该系统包括控制器，该控制器被配置为动态地调整执行一系列数据传送操作所需的通信的交错，以最大限度地利用要进行通信的信道的利用。 控制器能够通过用与控制信息分开发送的选通信号通过信令数据传送的开始来改变请求数据传送的控制信息的传输与数据传送的执行之间的时间间隔。 控制器能够通过启动具有终止信号的数据传送的终止来推迟在操作中传送多少数据的确定。 该方法提供了用于区分同一行上承载的相同控制信号的技术。 该系统包括具有控制电路的存储器件，该控制电路允许不超过一个由任何给定电源线供电的存储体进行感测或预充电操作。