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1.发明授权公开(公告)号：US08831161B2
公开(公告)日：2014-09-09
申请号：US13223214
申请日：2011-08-31
CPC分类号： G06F13/14 , H04L12/281 , Y02D10/14
摘要： Methods and apparatus for adjusting the operation of a display device so as to be at least within prescribed form factor or other constraints. In one embodiment of the invention, various operational parameters for a display element are adjusted based on considerations specific to high density form factor constraints. For example, in one such device, a Low Power DisplayPort (LPDP) device having a LPDP source and sink adjust the data rate of the visual data to minimize power consumption while still properly supporting display panel resolutions. In some embodiments, the LPDP source and sink may adjust the transceiver voltages to minimize power consumption. In an alternate embodiment, an LPDP device adjusts data rates to minimize the effects of platform noise. In another aspect of the invention, various display elements of a device coordinate quiescent (“quiet”) mode operation during periods of inactivity.
摘要翻译： 用于调节显示装置的操作以至少在规定的形状因数或其他限制内的方法和装置。 在本发明的一个实施例中，用于显示元件的各种操作参数基于特定于高密度形状因子约束的考虑来调整。 例如，在一个这样的设备中，具有LPDP源和接收器的低功率显示端口（LPDP）设备调整视觉数据的数据速率以最小化功耗，同时仍然适当地支持显示面板分辨率。 在一些实施例中，LPDP源和接收器可以调整收发器电压以最小化功率消耗。 在替代实施例中，LPDP设备调整数据速率以最小化平台噪声的影响。 在本发明的另一方面，在不活动期间，设备坐标静止（“安静”）模式操作的各种显示元件。
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公开(公告)号：US08842714B2
公开(公告)日：2014-09-23
申请号：US13417078
申请日：2012-03-09
申请人： Moon Jung Kim , Geertjan Joordens , Paolo Sacchetto , Wonjae Choi , Altan N. Yazar , Jaydeep V. Ranade
发明人： Moon Jung Kim , Geertjan Joordens , Paolo Sacchetto , Wonjae Choi , Altan N. Yazar , Jaydeep V. Ranade
IPC分类号： H04B1/00
CPC分类号： H03L7/00 , H04B1/123 , H04B15/06 , H04B2215/067
摘要： An electronic device may contain clock circuits, transmitters, and other circuits that serve as sources of noise signals. The noise signals may be characterized by a noise spectrum. The noise spectrum produced by a noise source can be adjusted by adjusting spread spectrum clock circuitry in a clock circuit, by adjusting data scrambling circuitry in a transmitter circuit, or by making other dynamic adjustments to the circuitry of the electronic device. During operation of the electronic device, sensitive circuitry in the device such as wireless receiver circuitry may be adversely affected by the presence of noise from a noise source in the device. Based on information such as which receiver bands and/or channels are being actively received and target sensitivity levels for the receiver circuitry, control circuitry within the electronic device can determine in real time how to minimize interference between the noise source and the wireless receiver circuitry.
摘要翻译： 电子设备可以包含用作噪声信号源的时钟电路，发射器和其它电路。 噪声信号可以由噪声谱表征。 可以通过调整时钟电路中的扩频时钟电路，通过调整发射机电路中的数据加扰电路，或通过对电子设备的电路进行其他动态调整来调整由噪声源产生的噪声频谱。 在电子设备的操作期间，诸如无线接收器电路的设备中的敏感电路可能受到来自设备中的噪声源的噪声的存在的不利影响。 基于诸如接收机频带和/或频道被主动接收的信息以及接收机电路的目标灵敏度级别，电子设备内的控制电路可以实时地确定如何最小化噪声源和无线接收机电路之间的干扰。
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公开(公告)号：US09838165B2
公开(公告)日：2017-12-05
申请号：US11995603
申请日：2006-07-12
IPC分类号： H04L1/20 , G01R31/317 , G01R31/3193 , H04L1/24
CPC分类号： H04L1/205 , G01R31/31725 , G01R31/31937 , H04L1/242
摘要： A method of testing a data transmission and reception system comprises sending a test signal from a transmitter (14) of the system to a receiver (12) of the system, and analyzing the received signal. A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed. Varying the duty cycle relationship provides duty cycle distortion (DCD), and this can be considered as a form of embedded jitter insertion. This type of jitter can be measured relatively easily.
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4.发明申请公开(公告)号：US20130050216A1
公开(公告)日：2013-02-28
申请号：US13223214
申请日：2011-08-31
CPC分类号： G06F13/14 , H04L12/281 , Y02D10/14
摘要： Methods and apparatus for adjusting the operation of a display device so as to be at least within prescribed form factor or other constraints. In one embodiment of the invention, various operational parameters for a display element are adjusted based on considerations specific to high density form factor constraints. For example, in one such device, a Low Power DisplayPort (LPDP) device having a LPDP source and sink adjust the data rate of the visual data to minimize power consumption while still properly supporting display panel resolutions. In some embodiments, the LPDP source and sink may adjust the transceiver voltages to minimize power consumption. In an alternate embodiment, an LPDP device adjusts data rates to minimize the effects of platform noise. In another aspect of the invention, various display elements of a device coordinate quiescent (“quiet”) mode operation during periods of inactivity.
摘要翻译： 用于调节显示装置的操作以至少在规定的形状因数或其他限制内的方法和装置。 在本发明的一个实施例中，用于显示元件的各种操作参数基于特定于高密度形状因子约束的考虑来调整。 例如，在一个这样的设备中，具有LPDP源和接收器的低功率显示端口（LPDP）设备调整视觉数据的数据速率以最小化功耗，同时仍然适当地支持显示面板分辨率。 在一些实施例中，LPDP源和接收器可以调整收发器电压以最小化功率消耗。 在替代实施例中，LPDP设备调整数据速率以最小化平台噪声的影响。 在本发明的另一方面，在不活动期间，设备坐标静止（安静）模式操作的各种显示元件。
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公开(公告)号：US20080270818A1
公开(公告)日：2008-10-30
申请号：US12089251
申请日：2006-10-09
申请人： Geertjan Joordens
发明人： Geertjan Joordens
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A communication interface for use in an integrated circuit comprises a clock root circuit (110) configured to receive the clock reference signal and to generate a clock tree signal. A first lane circuit (220b) is coupled to the clock root circuit and configured to receive the clock tree signal and a select signal for selecting a clock signal for a first interface circuit. A second lane circuit (220a) is coupled to the first lane circuit and configured to receive the clock tree signal and a select signal for selecting a clock signal for a second interface circuit. In one embodiment, each lane circuit includes a buffer (222) configured to receive the clock tree signal and a multiplexer (228) configured to selectively deliver the clock tree signal to the interface circuit. Advantages of the invention include a modular construction of a communication interface having low clock skew.
摘要翻译： 用于集成电路的通信接口包括被配置为接收时钟参考信号并产生时钟树信号的时钟根电路（110）。 第一通道电路（220b）耦合到时钟根电路并且被配置为接收时钟树信号和用于选择用于第一接口电路的时钟信号的选择信号。 第二通道电路（220a）耦合到第一通道电路并且被配置为接收时钟树信号和用于选择用于第二接口电路的时钟信号的选择信号。 在一个实施例中，每个通道电路包括被配置为接收时钟树信号的缓冲器（222）和经配置以选择性地将时钟树信号传递到接口电路的多路复用器（228）。 本发明的优点包括具有低时钟偏差的通信接口的模块化结构。
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6.发明授权公开(公告)号：US07236551B2
公开(公告)日：2007-06-26
申请号：US10259537
申请日：2002-09-27
IPC分类号： H04L7/00
CPC分类号： H03K5/1252 , H03D13/004 , H03L7/081 , H03L7/089 , H03L7/0891 , H04L7/033
摘要： There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of −90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.
摘要翻译： 有一个时钟恢复电路来校正数据信号和时钟信号之间的时序关系。 时钟恢复电路包括相位检测器，具有用于接收具有周期的时钟信号的输入端，用于接收数据信号的输入端和用于接收窗口信号的输入端。 窗口信号的周期等于时钟信号的周期，相对于时钟信号的相位差为-90°。 相位检测器响应于时钟信号和数据信号之间的相位关系，产生上输出和下输出，同时保持上输出和下输出的相位关系。
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公开(公告)号：US20130235906A1
公开(公告)日：2013-09-12
申请号：US13417078
申请日：2012-03-09
申请人： Moon Jung Kim , Geertjan Joordens , Paolo Sacchetto , Wonjae Choi , Altan N. Yazar , Jaydeep V. Ranade
发明人： Moon Jung Kim , Geertjan Joordens , Paolo Sacchetto , Wonjae Choi , Altan N. Yazar , Jaydeep V. Ranade
IPC分类号： H04B1/7097 , H04L25/08 , H04B15/00
CPC分类号： H03L7/00 , H04B1/123 , H04B15/06 , H04B2215/067
摘要： An electronic device may contain clock circuits, transmitters, and other circuits that serve as sources of noise signals. The noise signals may be characterized by a noise spectrum. The noise spectrum produced by a noise source can be adjusted by adjusting spread spectrum clock circuitry in a clock circuit, by adjusting data scrambling circuitry in a transmitter circuit, or by making other dynamic adjustments to the circuitry of the electronic device. During operation of the electronic device, sensitive circuitry in the device such as wireless receiver circuitry may be adversely affected by the presence of noise from a noise source in the device. Based on information such as which receiver bands and/or channels are being actively received and target sensitivity levels for the receiver circuitry, control circuitry within the electronic device can determine in real time how to minimize interference between the noise source and the wireless receiver circuitry.
摘要翻译： 电子设备可以包含用作噪声信号源的时钟电路，发射器和其它电路。 噪声信号可以由噪声谱表征。 可以通过调整时钟电路中的扩频时钟电路，通过调整发射机电路中的数据加扰电路，或通过对电子设备的电路进行其他动态调整来调整由噪声源产生的噪声频谱。 在电子设备的操作期间，诸如无线接收器电路的设备中的敏感电路可能受到来自设备中的噪声源的噪声的存在的不利影响。 基于诸如接收机频带和/或频道被主动接收的信息以及接收机电路的目标灵敏度级别，电子设备内的控制电路可以实时地确定如何最小化噪声源和无线接收机电路之间的干扰。
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8.发明申请公开(公告)号：US20090105978A1
公开(公告)日：2009-04-23
申请号：US11995603
申请日：2006-07-12
IPC分类号： G01R29/26
CPC分类号： H04L1/205 , G01R31/31725 , G01R31/31937 , H04L1/242
摘要： A method of testing a data transmission and reception system comprises sending a test signal from a transmitter (14) of the system to a receiver (12) of the system, and analyzing the received signal. A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed. Varying the duty cycle relationship provides duty cycle distortion (DCD), and this can be considered as a form of embedded jitter insertion. This type of jitter can be measured relatively easily.
摘要翻译： 一种测试数据传输和接收系统的方法包括将测试信号从系统的发射机（14）发送到系统的接收机（12），并分析接收到的信号。 测试信号与系统接收机使用的定时信号之间的占空比关系不同，分析了占空比变化的影响。 改变占空比关系提供占空比失真（DCD），这可以被认为是嵌入式抖动插入的一种形式。 这种类型的抖动可以相对容易地测量。
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公开(公告)号：US20080258781A1
公开(公告)日：2008-10-23
申请号：US11994229
申请日：2006-06-30
申请人： Wenyi Song , Geertjan Joordens
发明人： Wenyi Song , Geertjan Joordens
IPC分类号： H03B19/00
CPC分类号： H03K23/665 , H03K23/425 , H03K23/542
摘要： A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at the end of every output clock. Each divisor bit is gated to a D-input through a respective data multiplexer controlled by a clock output. A run/initialize mode controller receives the input frequency and produces the divided output frequency and controls the timing of the re-initialization.
摘要翻译： 一个多位可编程模块化数字分频器将输入频率除以m位整数除数以产生输出频率。 整数除数在每个输出时钟结束时用除数输入重新初始化M个触发器级。 每个除数位通过由时钟输出控制的相应数据复用器选通D输入。 运行/初始化模式控制器接收输入频率并产生分频输出频率并控制重新初始化的时序。
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