公开(公告)号：US08553754B2

公开(公告)日：2013-10-08

申请号：US12973242

申请日：2010-12-20

申请人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

发明人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

IPC分类号： H03K5/159 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03878 ,  H04L25/03057

摘要： A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.

摘要翻译： 提供了一种判决反馈均衡（DFE）接收机和方法。 DFE接收器配置为从数据总线采样数据位。 DFE接收器包括数据采样器，其被配置为使用第一，第二和第三参考电压之一从数据总线采样当前数据位。 DFE接收机还包括被配置为基于先前的数据总线电平来选择第一，第二和第三电压基准之一的多路复用逻辑。 其中如果先前数据总线电平为逻辑0，则选择第一参考电压。 如果先前的数据总线电平为逻辑1，则选择第二个参考电压。 如果先前的数据总线电平为三态，则选择第三个参考电压。

公开(公告)号：US07929549B1

公开(公告)日：2011-04-19

申请号：US11368786

申请日：2006-03-06

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： H04L12/40 ,  G06F12/14 ,  H04L9/00

CPC分类号： H04L12/40013 ,  H04L9/0662

摘要： A memory subsystem includes a master controller that includes a pseudo random bit sequence (PRBS) generator having a plurality of output taps and an exclusive-OR (XOR) unit. The memory subsystem also includes a memory device that is coupled to the master controller via a plurality of single ended bidirectional data paths. The master controller may scramble a plurality of data bits using the PRBS generator and the XOR unit prior to writing the plurality of data bits to the memory device. In addition, the master controller may perform an XOR between each bit of the plurality of data bits and a respective output tap of the PRBS generator prior to conveyance on a respective path of the plurality of single ended bidirectional data paths.

摘要翻译： 存储器子系统包括主控制器，其包括具有多个输出抽头和异或（XOR）单元的伪随机位序列（PRBS）生成器。 存储器子系统还包括经由多个单端双向数据路径耦合到主控制器的存储器件。 在将多个数据位写入存储器件之前，主控制器可以使用PRBS发生器和XOR单元来加扰多个数据位。 此外，主控制器可以在多个单端双向数据路径的相应路径上传输之前，在多个数据位的每一位和PRBS发生器的相应输出抽头之间执行XOR。

公开(公告)号：US07561625B1

公开(公告)日：2009-07-14

申请号：US11348136

申请日：2006-02-06

申请人： Shawn Searles ,  Gerald R. Talbot

发明人： Shawn Searles ,  Gerald R. Talbot

IPC分类号： H04B3/00

CPC分类号： H04B3/32

摘要： A method and apparatus for crosstalk reduction. In one embodiment, an electronic system includes a transmitter and a receiver coupled by a plurality of differential signal paths. A first differential signal path is adjacent to a second differential signal path, which is adjacent to a third. Data transmitted on a first differential signal path is scrambled with a first scrambler function, while data transmitted on a third differential signal path is scrambled with a second scrambler function, which is an inverse of the first scrambler function. Data transmitted on a second differential signal path is scrambled with a third scrambler function, while data transmitted on a fourth differential signal path is scrambled with a fourth scrambler function that is an inverse of the third.

摘要翻译： 一种用于串扰减少的方法和装置。 在一个实施例中，电子系统包括通过多个差分信号路径耦合的发射机和接收机。 第一差分信号路径与与第三差分信号路径相邻的第二差分信号路径相邻。 在第一差分信号路径上发送的数据用第一加扰器功能进行加扰，而在第三差分信号路径上发送的数据被加扰，第二加扰器功能是第一加扰器功能的倒数。 在第二差分信号路径上发送的数据用第三加扰器功能进行加扰，而在第四差分信号路径上发送的数据用与第三差分信号路径相反的第四加扰器功能进行加扰。

公开(公告)号：US07506222B1

公开(公告)日：2009-03-17

申请号：US11368792

申请日：2006-03-06

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： G06F11/00

CPC分类号： G06F11/1004 ,  H04L1/0057

摘要： A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths. The master device may adaptively modify transmit characteristics based upon data eye information sent via one or more unidirectional data paths by the slave device. The data eye information may correspond to an edge position of data signal transitions received by the slave device on each data path of the plurality of bidirectional data paths. In addition, the master device may modify data path equalization coefficients within the master device for a grouping of the bidirectional data paths such as a byte group, for example, dependent upon the data eye information.

摘要翻译： 用于高速双向信令的非对称控制的用于字节组的相位跟踪和均衡的系统包括从设备和通过多个双向数据路径耦合到从设备的主设备。 主设备可以基于从设备经由一个或多个单向数据路径发送的数据眼信息来自适应地修改发送特性。 数据眼信息可以对应于从设备在多个双向数据路径的每个数据路径上接收的数据信号转换的边缘位置。 此外，主设备可以修改主设备内的数据路径均衡系数，用于例如依赖于数据眼睛信息的诸如字节组的双向数据路径的分组。

公开(公告)号：US07505332B1

公开(公告)日：2009-03-17

申请号：US11368773

申请日：2006-03-06

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： G11C7/00

CPC分类号： H04L25/03343 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/08 ,  H04L25/06 ,  H04L2001/0094

摘要： A system including input offset correction for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device. The master device may control data transfer between the master device and the slave device. In response to the master device determining there is an input offset bias present within the slave device, the master device may adaptively modify a DC voltage offset of data transmitted by the master device based upon data eye information received from the slave device via one or more unidirectional signal paths.

摘要翻译： 包括用于非对称控制高速双向信令的输入偏移校正的系统包括耦合到从设备的从设备和主设备。 主设备可以控制主设备和从设备之间的数据传输。 响应于主设备确定在从设备中存在输入偏移偏移，主设备可以基于从从设备经由一个或多个接收到的数据眼信息自适应地修改由主设备发送的数据的DC电压偏移 单向信号路径。

公开(公告)号：US20080126909A1

公开(公告)日：2008-05-29

申请号：US11518842

申请日：2006-09-11

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： H03M13/00 ,  G06F15/16

CPC分类号： G06F13/4243 ,  G06F11/1076 ,  H04L1/0061 ,  H04L1/14 ,  H04L7/041

摘要： A system for protecting data during high-speed bidirectional communication between a master device and a slave device. The master device may control data transfer between the master device and the slave device. In addition, the master device may perform a read request to the slave device for a first data block associated with a first address and a second data block associated with a second address. In response, the slave device may send to the master device a portion of the first data block in a first burst and a portion of the second data block in a second burst via a plurality of bidirectional data paths. The slave device may further generate and send to the master device via one or more unidirectional data paths a cyclic redundancy code (CRC) based upon the first data block and the second data block.

摘要翻译： 一种用于在主设备和从设备之间的高速双向通信期间保护数据的系统。 主设备可以控制主设备和从设备之间的数据传输。 此外，主设备可以向从设备执行与第一地址相关联的第一数据块的读请求和与第二地址相关联的第二数据块的读请求。 作为响应，从设备可以经由多个双向数据路径在第一突发中向主设备发送第一数据块的一部分和第二突发中的第二数据块的一部分。 从设备还可以经由一个或多个单向数据路径生成并基于第一数据块和第二数据块向循环冗余码（CRC）发送循环冗余码（CRC）。

公开(公告)号：US4769632A

公开(公告)日：1988-09-06

申请号：US828208

申请日：1986-02-10

申请人： Gordon S. Work ,  Gerald R. Talbot

发明人： Gordon S. Work ,  Gerald R. Talbot

IPC分类号： G09G5/02 ,  G09G1/28 ,  G09G5/06 ,  H03M1/68

CPC分类号： G09G5/06

摘要： A color graphics control system for generating red, blue and green analog signals to a raster scan display at a pixel frequency comprises a RAM storing a pluraltiy of digital color values, digital to analog converters for converting the digital color values into analog signals, an interface to permit an external controller to write digital color values into the RAM locations, a timer including a pixel clock and RAM accessing means controlled by the timer to pipeline RAM accessing with a cycle time of more than one pixel period.

摘要翻译： 用于以像素频率向光栅扫描显示产生红色，蓝色和绿色模拟信号的彩色图形控制系统包括存储多个数字颜色值的RAM，用于将数字颜色值转换为模拟信号的数模转换器，接口 允许外部控制器将数字颜色值写入RAM位置，定时器包括由定时器控制的像素时钟和RAM存取装置，以便以多于一个像素周期的周期时间流水线RAM访问。

公开(公告)号：US08760946B2

公开(公告)日：2014-06-24

申请号：US13477642

申请日：2012-05-22

申请人： Glenn A Dearth ,  Warren R Anderson ,  Anwar P Kashem ,  Richard W Reeves ,  Edoardo Prete ,  Gerald R Talbot

发明人： Glenn A Dearth ,  Warren R Anderson ,  Anwar P Kashem ,  Richard W Reeves ,  Edoardo Prete ,  Gerald R Talbot

IPC分类号： G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076

摘要： Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.

摘要翻译： 公开了用于训练用于在存储器子系统中启用数据选通信号的延迟的各种方法和装置实施例。 在一个实施例中，系统包括被配置为接收数据选通信号的存储器控​​制器。 存储器控制器包括训练电路。 训练电路包括：第一存储电路，被耦合以在数据输入端接收数据选通信号;以及训练单元，被配置为基于从第一触发器接收到的输出信号调整一个 使能信号的相位直到使能信号的断言与数据选通信号中的前导码指示一致。

公开(公告)号：US08000404B2

公开(公告)日：2011-08-16

申请号：US11627586

申请日：2007-01-26

申请人： Gerald R. Talbot ,  Paul C. Miranda

发明人： Gerald R. Talbot ,  Paul C. Miranda

IPC分类号： H04B15/00

CPC分类号： H04L25/03866 ,  H04L25/085 ,  H04L25/45

摘要： A technique for reducing crosstalk between communications paths includes scrambling data using scrambling functions that reduce or substantially minimize a probability that worst-case data patterns occur on communications paths adjacent to a potential victim communications path. In at least one embodiment of the invention, a method includes scrambling a plurality of data bits based at least in part on respective ones of a plurality of distinct combinations of one or more taps of a linear feedback shift register (LFSR). The plurality of data bits are scrambled for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths.

摘要翻译： 用于减少通信路径之间的串扰的技术包括使用减少或基本上最小化最差情况数据模式在与潜在受害者通信路径相邻的通信路径上发生的概率的加扰数据的加扰数据。 在本发明的至少一个实施例中，一种方法包括至少部分地基于线性反馈移位寄存器（LFSR）的一个或多个抽头的多个不同组合中的相应的数据位来对多个数据位进行加扰。 多个数据比特被加扰以便在多个相邻通信路径中的相应的一个的第一比特时间内进行传输。

公开(公告)号：US20080104352A1

公开(公告)日：2008-05-01

申请号：US11590285

申请日：2006-10-31

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： G06F13/00

CPC分类号： G06F13/1673 ,  G06F13/1684 ,  G06F13/1689

摘要： A memory system includes one or more memory units, each including one or more memory devices and a parallel interconnect. The system also includes a memory controller that may control data transfer between the memory controller and the memory units. The memory system further includes one or more buffer units that are coupled to the memory units via the parallel interconnect. Each of the buffer units is coupled to the memory controller via a respective serial interconnect. Each buffer unit may, in response to receiving command information from the memory controller, receive data from the memory controller via the respective serial interconnect, and also transmit the data to the memory units via the parallel interconnect. The memory controller may further asymmetrically control data transfer between the memory controller and the buffer units by adjusting signal characteristics of transmitted data based upon information received from the buffer units.

摘要翻译： 存储器系统包括一个或多个存储器单元，每个存储器单元包括一个或多个存储器件和并行互连。 该系统还包括可以控制存储器控制器和存储器单元之间的数据传输的存储器控​​制器。 存储器系统还包括一个或多个缓冲器单元，其通过并行互连耦合到存储器单元。 每个缓冲单元通过相应的串行互连耦合到存储器控制器。 每个缓冲器单元可以响应于来自存储器控制器的接收命令信息经由相应的串行互连从存储器控制器接收数据，并且还经由并行互连将数据发送到存储器单元。 存储器控制器还可以通过基于从缓冲器单元接收的信息调整发送数据的信号特性来不对称地控制存储器控制器和缓冲器单元之间的数据传输。