摘要:
A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel. In addition, a data interconnection unit is configured to shift the plurality of data output from the memory and provide the shifted data to a plurality of operation units as input data. The operation result from each of the plurality of operation units is stored in a region of the memory.
摘要:
A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.
摘要:
An integrated circuit device is provided with a power supply voltage generator therein. This voltage generator is configured to respond to an operating mode control signal by generating first and second power supply voltages at equivalent voltage levels when the operating mode control signal designates a normal mode of operation within the integrated circuit device. The power supply voltage generator is also configured to reduce the first and second power supply voltages to unequal lower voltage levels when the operating mode control signal designates a power saving mode of operation within the integrated circuit device. The power supply voltage generator may also generate a third power supply voltage at a constant level during both the normal and power saving modes of operation.
摘要:
A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.
摘要:
An image search method may include: determining a quadrant of a predicted motion vector; calculating a tilt value of a first reference frame and a tilt value of a second reference frame using the predicted motion vector; deciding a search area for uneven hexagon search in response to the quadrant of the predicted motion vector and the calculated tilt values; performing the uneven hexagon search with respect to the decided search area; and/or comparing a result of the performed uneven hexagon search with a threshold value to determine termination of the uneven hexagon search. The second reference frame is earlier-in-time relative to the first reference frame.
摘要:
A branch target buffer, a branch prediction circuit and a method thereof are provided. The example branch target buffer may include a memory cell array storing a branch address and a target address, a decoder connected to the memory cell array through a word line, and providing a word line voltage to a selected word line in response to a fetch address, a sense amp connected to the memory cell array through a bit line and sensing and amplifying data of a selected memory cell and sense amp enable circuitry connected to the word line, the sense amp enable circuitry storing branch prediction information and controlling an operation of the sense amp based on the branch prediction information. The example method may be directed to a method of operating a branch target buffer, including determining whether an instruction to be executed by a processor is a branch instruction, determining, if the instruction is determined to be a branch instruction, whether the branch instruction is predicted to be taken and selectively buffering instructions, from one or more memory cells, associated with the branch instruction based on whether the branch instruction is predicted to be taken.
摘要:
An integrated circuit device is provided with a power supply voltage generator therein. This voltage generator is configured to respond to an operating mode control signal by generating first and second power supply voltages at equivalent voltage levels when the operating mode control signal designates a normal mode of operation within the integrated circuit device. The power supply voltage generator is also configured to reduce the first and second power supply voltages to unequal lower voltage levels when the operating mode control signal designates a power saving mode of operation within the integrated circuit device. The power supply voltage generator may also generate a third power supply voltage at a constant level during both the normal and power saving modes of operation.
摘要:
Dynamic Frequency Scaling (DFS) cache memories that can be accessed during an idle time in a single low frequency DFS clock cycle are disclosed. The access can begin during the idle time in the single low frequency DFS clock cycle and may continue during a subsequent low frequency DFS clock cycle. The idle time can be a time interval in the single low frequency DFS clock cycle between completion of a single high frequency DFS clock cycle and completion of the single low frequency DFS clock cycle. Related circuits and systems are also disclosed.
摘要:
A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.
摘要:
An image search method may include: determining a quadrant of a predicted motion vector; calculating a tilt value of a first reference frame and a tilt value of a second reference frame using the predicted motion vector; deciding a search area for uneven hexagon search in response to the quadrant of the predicted motion vector and the calculated tilt values; performing the uneven hexagon search with respect to the decided search area; and/or comparing a result of the performed uneven hexagon search with a threshold value to determine termination of the uneven hexagon search. The second reference frame is earlier-in-time relative to the first reference frame.