Memory array structure and single instruction multiple data processor including the same and methods thereof
    1.
    发明授权
    Memory array structure and single instruction multiple data processor including the same and methods thereof 有权
    内存阵列结构和单指令多数据处理器包括相同的方法

    公开(公告)号:US07725641B2

    公开(公告)日:2010-05-25

    申请号:US11806593

    申请日:2007-06-01

    IPC分类号: G06F12/00

    CPC分类号: G06F15/8015

    摘要: A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel. In addition, a data interconnection unit is configured to shift the plurality of data output from the memory and provide the shifted data to a plurality of operation units as input data. The operation result from each of the plurality of operation units is stored in a region of the memory.

    摘要翻译: 存储器可以被配置为重新排列和存储数据,以便为编码器 - 解码器(编解码器)所需的存储器访问模式实现无冲突模式,并被配置为并行地从存储器的多个存储体中输出多个数据。 此外,数据互连单元被配置为移位从存储器输出的多个数据,并将移位的数据提供给多个操作单元作为输入数据。 来自多个操作单元中的每一个的操作结果被存储在存储器的区域中。

    Branch target buffer and method of use
    2.
    发明授权
    Branch target buffer and method of use 有权
    分支目标缓冲区和使用方法

    公开(公告)号:US07609582B2

    公开(公告)日:2009-10-27

    申请号:US12052762

    申请日:2008-03-21

    申请人: Gi Ho Park

    发明人: Gi Ho Park

    IPC分类号: G11C8/00

    CPC分类号: G06F9/3806 G06F9/3844

    摘要: A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.

    摘要翻译: 公开了存储与分支指令相关的数据条目的转移目标缓冲器(BTB)。 BTB有条件地使得能够响应于与BTB中的字线相关联的字线选通电路来访问数据条目。 字线选通电路存储从与指令相关的分支历史数据导出的字线门控值。 此外,公开了分支预测单元和结合BTB的处理器以及用于操作BTB的方法。

    Integrated circuit devices that support dynamic voltage scaling of power supply voltages
    3.
    发明授权
    Integrated circuit devices that support dynamic voltage scaling of power supply voltages 有权
    支持电源电压动态电压缩放的集成电路器件

    公开(公告)号:US07412613B2

    公开(公告)日:2008-08-12

    申请号:US11060838

    申请日:2005-02-18

    申请人: Gi-ho Park

    发明人: Gi-ho Park

    IPC分类号: G06F1/32 G06F1/00

    摘要: An integrated circuit device is provided with a power supply voltage generator therein. This voltage generator is configured to respond to an operating mode control signal by generating first and second power supply voltages at equivalent voltage levels when the operating mode control signal designates a normal mode of operation within the integrated circuit device. The power supply voltage generator is also configured to reduce the first and second power supply voltages to unequal lower voltage levels when the operating mode control signal designates a power saving mode of operation within the integrated circuit device. The power supply voltage generator may also generate a third power supply voltage at a constant level during both the normal and power saving modes of operation.

    摘要翻译: 在其中设置有电源电压发生器的集成电路装置。 该电压发生器被配置为当操作模式控制信号指定集成电路装置内的正常操作模式时,通过以等效电压电平产生第一和第二电源电压来响应工作模式控制信号。 电源电压发生器还被配置为当操作模式控制信号指定集成电路装置内的省电模式时,将第一和第二电源电压减小到不等的较低电压电平。 电源电压发生器还可以在正常和省电操作模式期间产生恒定电平的第三电源电压。

    BRANCH TARGET BUFFER AND METHOD OF USE
    4.
    发明申请
    BRANCH TARGET BUFFER AND METHOD OF USE 有权
    分支目标缓冲区和使用方法

    公开(公告)号:US20080168263A1

    公开(公告)日:2008-07-10

    申请号:US12052762

    申请日:2008-03-21

    申请人: Gi Ho Park

    发明人: Gi Ho Park

    IPC分类号: G06F9/30

    CPC分类号: G06F9/3806 G06F9/3844

    摘要: A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.

    摘要翻译: 公开了存储与分支指令相关的数据条目的转移目标缓冲器(BTB)。 BTB有条件地使得能够响应于与BTB中的字线相关联的字线选通电路来访问数据条目。 字线选通电路存储从与指令相关的分支历史数据导出的字线门控值。 此外,公开了分支预测单元和结合BTB的处理器以及用于操作BTB的方法。

    Image search methods for reducing computational complexity of motion estimation
    5.
    发明申请
    Image search methods for reducing computational complexity of motion estimation 有权
    用于降低运动估计的计算复杂度的图像搜索方法

    公开(公告)号:US20080112487A1

    公开(公告)日:2008-05-15

    申请号:US11730278

    申请日:2007-03-30

    IPC分类号: H04N11/02

    摘要: An image search method may include: determining a quadrant of a predicted motion vector; calculating a tilt value of a first reference frame and a tilt value of a second reference frame using the predicted motion vector; deciding a search area for uneven hexagon search in response to the quadrant of the predicted motion vector and the calculated tilt values; performing the uneven hexagon search with respect to the decided search area; and/or comparing a result of the performed uneven hexagon search with a threshold value to determine termination of the uneven hexagon search. The second reference frame is earlier-in-time relative to the first reference frame.

    摘要翻译: 图像搜索方法可以包括:确定预测运动矢量的象限; 使用所述预测运动矢量来计算第一参考帧的倾斜值和第二参考帧的倾斜值; 响应于预测运动矢量的象限和计算的倾斜值,确定不均匀六边形搜索的搜索区域; 执行相对于所决定的搜索区域的不均匀六边形搜索; 和/或将执行的不均匀六边形搜索的结果与阈值进行比较,以确定不均匀六边形搜索的终止。 第二参考帧相对于第一参考帧是较早的时间。

    Branch target buffer, a branch prediction circuit and method thereof
    6.
    发明申请
    Branch target buffer, a branch prediction circuit and method thereof 审中-公开
    分支目标缓冲器,分支预测电路及其方法

    公开(公告)号:US20070192574A1

    公开(公告)日:2007-08-16

    申请号:US11700780

    申请日:2007-02-01

    申请人: Gi-Ho Park

    发明人: Gi-Ho Park

    IPC分类号: G06F9/00

    摘要: A branch target buffer, a branch prediction circuit and a method thereof are provided. The example branch target buffer may include a memory cell array storing a branch address and a target address, a decoder connected to the memory cell array through a word line, and providing a word line voltage to a selected word line in response to a fetch address, a sense amp connected to the memory cell array through a bit line and sensing and amplifying data of a selected memory cell and sense amp enable circuitry connected to the word line, the sense amp enable circuitry storing branch prediction information and controlling an operation of the sense amp based on the branch prediction information. The example method may be directed to a method of operating a branch target buffer, including determining whether an instruction to be executed by a processor is a branch instruction, determining, if the instruction is determined to be a branch instruction, whether the branch instruction is predicted to be taken and selectively buffering instructions, from one or more memory cells, associated with the branch instruction based on whether the branch instruction is predicted to be taken.

    摘要翻译: 提供了分支目标缓冲器,分支预测电路及其方法。 示例性分支目标缓冲器可以包括存储分支地址和目标地址的存储单元阵列,通过字线连接到存储单元阵列的解码器,以及响应于提取地址向选定字线提供字线电压 ,通过位线连接到存储单元阵列的感测放大器,感测和放大所选存储单元的数据和连接到字线的感测放大器使能电路,读出放大器使能电路存储分支预测信息并控制 基于分支预测信息的感测放大器。 该示例方法可以涉及一种操作分支目标缓冲器的方法,包括确定由处理器执行的指令是否是分支指令,确定该指令是否为分支指令,分支指令是否为 预测将基于是否预测分支指令被采取并选择性地缓冲与分支指令相关联的一个或多个存储器单元的指令。

    Integrated circuit devices that support dynamic voltage scaling of power supply voltages
    7.
    发明申请
    Integrated circuit devices that support dynamic voltage scaling of power supply voltages 有权
    支持电源电压动态电压缩放的集成电路器件

    公开(公告)号:US20050188233A1

    公开(公告)日:2005-08-25

    申请号:US11060838

    申请日:2005-02-18

    申请人: Gi-ho Park

    发明人: Gi-ho Park

    摘要: An integrated circuit device is provided with a power supply voltage generator therein. This voltage generator is configured to respond to an operating mode control signal by generating first and second power supply voltages at equivalent voltage levels when the operating mode control signal designates a normal mode of operation within the integrated circuit device. The power supply voltage generator is also configured to reduce the first and second power supply voltages to unequal lower voltage levels when the operating mode control signal designates a power saving mode of operation within the integrated circuit device. The power supply voltage generator may also generate a third power supply voltage at a constant level during both the normal and power saving modes of operation.

    摘要翻译: 在其中设置有电源电压发生器的集成电路装置。 该电压发生器被配置为当操作模式控制信号指定集成电路装置内的正常操作模式时,通过以等效电压电平产生第一和第二电源电压来响应工作模式控制信号。 电源电压发生器还被配置为当操作模式控制信号指定集成电路装置内的省电模式时,将第一和第二电源电压减小到不等的较低电压电平。 电源电压发生器还可以在正常和省电操作模式期间产生恒定电平的第三电源电压。

    Methods, circuits, and systems for utilizing idle time in dynamic frequency scaling cache memories
    8.
    发明申请
    Methods, circuits, and systems for utilizing idle time in dynamic frequency scaling cache memories 有权
    用于在动态频率缩放缓存存储器中利用空闲时间的方法,电路和系统

    公开(公告)号:US20050015553A1

    公开(公告)日:2005-01-20

    申请号:US10801893

    申请日:2004-03-16

    申请人: Gi-ho Park

    发明人: Gi-ho Park

    摘要: Dynamic Frequency Scaling (DFS) cache memories that can be accessed during an idle time in a single low frequency DFS clock cycle are disclosed. The access can begin during the idle time in the single low frequency DFS clock cycle and may continue during a subsequent low frequency DFS clock cycle. The idle time can be a time interval in the single low frequency DFS clock cycle between completion of a single high frequency DFS clock cycle and completion of the single low frequency DFS clock cycle. Related circuits and systems are also disclosed.

    摘要翻译: 公开了在单个低频DFS时钟周期中可以在空闲时间期间访问的动态频率缩放(DFS)高速缓存存储器。 访问可以在单个低频DFS时钟周期的空闲时间期间开始,并且可以在随后的低频DFS时钟周期期间继续。 在完成单个高频DFS时钟周期和完成单个低频DFS时钟周期之间,空闲时间可以是单个低频DFS时钟周期中的时间间隔。 还公开了相关电路和系统。

    Image search methods for reducing computational complexity of motion estimation
    10.
    发明授权
    Image search methods for reducing computational complexity of motion estimation 有权
    用于降低运动估计的计算复杂度的图像搜索方法

    公开(公告)号:US08379712B2

    公开(公告)日:2013-02-19

    申请号:US11730278

    申请日:2007-03-30

    IPC分类号: H04N11/02 H04N7/26 G06K9/00

    摘要: An image search method may include: determining a quadrant of a predicted motion vector; calculating a tilt value of a first reference frame and a tilt value of a second reference frame using the predicted motion vector; deciding a search area for uneven hexagon search in response to the quadrant of the predicted motion vector and the calculated tilt values; performing the uneven hexagon search with respect to the decided search area; and/or comparing a result of the performed uneven hexagon search with a threshold value to determine termination of the uneven hexagon search. The second reference frame is earlier-in-time relative to the first reference frame.

    摘要翻译: 图像搜索方法可以包括:确定预测运动矢量的象限; 使用所述预测运动矢量来计算第一参考帧的倾斜值和第二参考帧的倾斜值; 响应于预测运动矢量的象限和所计算的倾斜值,确定不均匀六边形搜索的搜索区域; 执行相对于所决定的搜索区域的不均匀六边形搜索; 和/或将执行的不均匀六边形搜索的结果与阈值进行比较,以确定不均匀六边形搜索的终止。 第二参考帧相对于第一参考帧是较早的时间。