公开(公告)号：US20210375713A1

公开(公告)日：2021-12-02

申请号：US17222238

申请日：2021-04-05

Applicant: AARON ASHLEY HATHAWAY ,  GREGORY R. BOYD ,  JOHN X. PRZYBYSZ

Inventor： AARON ASHLEY HATHAWAY ,  GREGORY R. BOYD ,  JOHN X. PRZYBYSZ

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

公开(公告)号：US11333413B2

公开(公告)日：2022-05-17

申请号：US16554203

申请日：2019-08-28

Applicant: Robert Miles Young ,  Aaron Ashley Hathaway ,  John X. Przybysz ,  Gregory R. Boyd ,  Zachary A. Stegen ,  Edward R. Engbrecht ,  Aaron A. Pesetski ,  Marc Eisenzweig Sherwin

Inventor： Robert Miles Young ,  Aaron Ashley Hathaway ,  John X. Przybysz ,  Gregory R. Boyd ,  Zachary A. Stegen ,  Edward R. Engbrecht ,  Aaron A. Pesetski ,  Marc Eisenzweig Sherwin

IPC: F25B21/00 ,  F25D31/00 ,  H01L39/06 ,  H01L23/00

Abstract: A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.

公开(公告)号：US10097186B1

公开(公告)日：2018-10-09

申请号：US15910254

申请日：2018-03-02

Applicant: Ryan J. Epstein ,  David James Clarke ,  Alexander Marakov ,  Gregory R. Boyd ,  Anthony Joseph Przybysz ,  Joel D. Strand ,  David George Ferguson

Inventor： Ryan J. Epstein ,  David James Clarke ,  Alexander Marakov ,  Gregory R. Boyd ,  Anthony Joseph Przybysz ,  Joel D. Strand ,  David George Ferguson

IPC: H03K19/195 ,  G06N99/00 ,  H03K3/38 ,  H03K19/16

Abstract: Systems and methods are provided for linking two components in a superconducting circuit. A plurality of circuit elements, each comprising one of an inductor, a capacitor, and a Josephson junction, are connected in series on a path connecting the two components. A plurality of tunable oscillators are connected from the path connecting the two components. Each tunable oscillator is responsive to a control signal to tune an associated resonance frequency of the tunable oscillator within a first frequency range, within which the two components are coupled, and within a second frequency range, within which the two components are isolated.

公开(公告)号：US20240355701A1

公开(公告)日：2024-10-24

申请号：US18630530

申请日：2024-04-09

Applicant: AARON ASHLEY HATHAWAY ,  GREGORY R. BOYD ,  JOHN X. PRZYBYSZ

Inventor： AARON ASHLEY HATHAWAY ,  GREGORY R. BOYD ,  JOHN X. PRZYBYSZ

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

CPC classification number: H01L23/367 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53285 ,  H01L23/66 ,  H01L2223/6605 ,  H01L2223/6683

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

公开(公告)号：US12027437B2

公开(公告)日：2024-07-02

申请号：US17222238

申请日：2021-04-05

Applicant: Aaron Ashley Hathaway ,  Gregory R. Boyd ,  John X. Przybysz

Inventor： Aaron Ashley Hathaway ,  Gregory R. Boyd ,  John X. Przybysz

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

CPC classification number: H01L23/367 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53285 ,  H01L23/66 ,  H01L2223/6605 ,  H01L2223/6683

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

公开(公告)号：US11004763B2

公开(公告)日：2021-05-11

申请号：US16227965

申请日：2018-12-20

Applicant: Aaron Ashley Hathaway ,  Gregory R. Boyd ,  John X. Przybysz

Inventor： Aaron Ashley Hathaway ,  Gregory R. Boyd ,  John X. Przybysz

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

公开(公告)号：US20210063060A1

公开(公告)日：2021-03-04

申请号：US16554203

申请日：2019-08-28

Applicant: Robert Miles Young ,  Aaron Ashley Hathaway ,  John X. Przybysz ,  Gregory R. Boyd ,  Zachary A. Stegen ,  Edward R. Engbrecht ,  Aaron A. Pesetski ,  Marc Eisenzweig Sherwin

Inventor： Robert Miles Young ,  Aaron Ashley Hathaway ,  John X. Przybysz ,  Gregory R. Boyd ,  Zachary A. Stegen ,  Edward R. Engbrecht ,  Aaron A. Pesetski ,  Marc Eisenzweig Sherwin

IPC: F25B21/00 ,  H01L39/06 ,  F25D31/00

Abstract: A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.