公开(公告)号：US20210063060A1

公开(公告)日：2021-03-04

申请号：US16554203

申请日：2019-08-28

Applicant: Robert Miles Young ,  Aaron Ashley Hathaway ,  John X. Przybysz ,  Gregory R. Boyd ,  Zachary A. Stegen ,  Edward R. Engbrecht ,  Aaron A. Pesetski ,  Marc Eisenzweig Sherwin

Inventor： Robert Miles Young ,  Aaron Ashley Hathaway ,  John X. Przybysz ,  Gregory R. Boyd ,  Zachary A. Stegen ,  Edward R. Engbrecht ,  Aaron A. Pesetski ,  Marc Eisenzweig Sherwin

IPC: F25B21/00 ,  H01L39/06 ,  F25D31/00

Abstract: A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.

公开(公告)号：US20190157184A1

公开(公告)日：2019-05-23

申请号：US16241629

申请日：2019-01-07

Applicant: PATRICK LONEY ,  ROBERT MILES YOUNG ,  DANIEL ROBERT QUEEN ,  AARON ASHLEY HATHAWAY ,  JOHN X. PRZYBYSZ

Inventor： PATRICK LONEY ,  ROBERT MILES YOUNG ,  DANIEL ROBERT QUEEN ,  AARON ASHLEY HATHAWAY ,  JOHN X. PRZYBYSZ

IPC: H01L23/433 ,  H05K1/02 ,  H01L27/18 ,  H01L23/373 ,  H01L23/367

Abstract: An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a first thermally conductive via that couples the first ground plane to the thermal sink layer. The circuit further comprises a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the thermal sink layer, wherein the first thermally conductive via has a greater volume of thermal conductive material than the second thermally conductive via to remove heat from the first set of circuits with less gradient than the second set of circuits.

公开(公告)号：US20190080983A1

公开(公告)日：2019-03-14

申请号：US15704919

申请日：2017-09-14

Applicant: PATRICK LONEY ,  ROBERT MILES YOUNG ,  DANIEL ROBERT QUEEN ,  AARON ASHLEY HATHAWAY ,  JOHN X. PRZYBYSZ

Inventor： PATRICK LONEY ,  ROBERT MILES YOUNG ,  DANIEL ROBERT QUEEN ,  AARON ASHLEY HATHAWAY ,  JOHN X. PRZYBYSZ

IPC: H01L23/433 ,  H01L23/373

Abstract: An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a first thermally conductive via that couples the first ground plane to the thermal sink layer. The circuit further comprises a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the thermal sink layer, wherein the first thermally conductive via has a greater volume of thermal conductive material than the second thermally conductive via to remove heat from the first set of circuits with less gradient than the second set of circuits.

公开(公告)号：US10229864B1

公开(公告)日：2019-03-12

申请号：US15704919

申请日：2017-09-14

Applicant: Patrick Loney ,  Robert Miles Young ,  Daniel Robert Queen ,  Aaron Ashley Hathaway ,  John X. Przybysz

Inventor： Patrick Loney ,  Robert Miles Young ,  Daniel Robert Queen ,  Aaron Ashley Hathaway ,  John X. Przybysz

IPC: H05K1/02 ,  H01L27/18 ,  H01L23/367 ,  H01L23/373 ,  H01L23/433

Abstract: An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a first thermally conductive via that couples the first ground plane to the thermal sink layer. The circuit further comprises a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the thermal sink layer, wherein the first thermally conductive via has a greater volume of thermal conductive material than the second thermally conductive via to remove heat from the first set of circuits with less gradient than the second set of circuits.

公开(公告)号：US07982646B2

公开(公告)日：2011-07-19

申请号：US12184204

申请日：2008-07-31

Applicant: Quentin P. Herr ,  Aaron A. Pesetski ,  John X. Przybysz ,  Donald L. Miller

Inventor： Quentin P. Herr ,  Aaron A. Pesetski ,  John X. Przybysz ,  Donald L. Miller

IPC: H03M3/00

CPC classification number: H03M3/454 ,  H03M3/422 ,  H03M3/47

Abstract: A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.

Abstract translation: 具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小 通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。 匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。 当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。

公开(公告)号：US5233242A

公开(公告)日：1993-08-03

申请号：US744728

申请日：1991-08-14

Applicant: John H. Murphy ,  Michael R. Daniel ,  John X. Przybysz

Inventor： John H. Murphy ,  Michael R. Daniel ,  John X. Przybysz

IPC: H03K19/195

CPC classification number: H03K19/1954

Abstract: Push-pull flux quantum gate array cells synchronously process a pair of polarized data signals. These polarized data signals can be derived from dual polarity data signals by separating the input signals into positive polarity data signals and negative polarity data signals. At least one logic or arithmetic operation is performed on each of the positive and negative polarity signals to produce modified positive and negative polarity signals respectively. These modified positive polarity and negative polarity signals can also be combined to produce a modified dual polarity output data signal. Numerous logic operations can be achieved in gate array cells which perform this signal processing method. By using push-pull flux quantum circuits, the need for auxiliary timing signals or interferometers is minimized.

Abstract translation: 推挽通量子门阵列单元同步处理一对极化数据信号。 这些极化数据信号可以通过将输入信号分离为正极性数据信号和负极性数据信号从双极性数据信号导出。 对正极性和负极性信号中的每一个执行至少一个逻辑或算术运算，以分别产生修正的正极性和负极性信号。 这些改正的正极性和负极性信号也可以组合以产生修改的双极性输出数据信号。 可以在执行该信号处理方法的门阵列单元中实现许多逻辑运算。 通过使用推挽通量量子电路，对辅助定时信号或干涉仪的需求最小化。

公开(公告)号：US11333413B2

公开(公告)日：2022-05-17

申请号：US16554203

申请日：2019-08-28

Applicant: Robert Miles Young ,  Aaron Ashley Hathaway ,  John X. Przybysz ,  Gregory R. Boyd ,  Zachary A. Stegen ,  Edward R. Engbrecht ,  Aaron A. Pesetski ,  Marc Eisenzweig Sherwin

Inventor： Robert Miles Young ,  Aaron Ashley Hathaway ,  John X. Przybysz ,  Gregory R. Boyd ,  Zachary A. Stegen ,  Edward R. Engbrecht ,  Aaron A. Pesetski ,  Marc Eisenzweig Sherwin

IPC: F25B21/00 ,  F25D31/00 ,  H01L39/06 ,  H01L23/00

Abstract: A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.

公开(公告)号：US10998485B1

公开(公告)日：2021-05-04

申请号：US16741341

申请日：2020-01-13

Applicant: John X. Przybysz ,  Robert M. Young ,  Aaron Ashley Hathaway ,  Edward R. Engbrecht ,  Monica P. Lilly

Inventor： John X. Przybysz ,  Robert M. Young ,  Aaron Ashley Hathaway ,  Edward R. Engbrecht ,  Monica P. Lilly

IPC: H01L39/18 ,  H01L39/02 ,  H01L23/00 ,  H01L39/24

Abstract: A solid state cooler device is disclosed that includes a first superconductor shunt, a first normal metal pad disposed on the first superconductor shunt, and a first insulator layer and a second insulator layer disposed on the normal metal pad and separated from one another by a gap. The solid state cooler device also includes a first superconductor pad disposed on the first insulator layer and a second superconductor pad disposed on the second insulator layer, a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad. Hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad, wherein the first superconductor shunt facilitates even current distribution through the device.

公开(公告)号：US5327130A

公开(公告)日：1994-07-05

申请号：US103844

申请日：1993-08-09

Applicant: Joonhee Kang ,  John X. Przybysz ,  Donald L. Miller

Inventor： Joonhee Kang ,  John X. Przybysz ,  Donald L. Miller

IPC: G01R13/34 ,  H03K5/24 ,  H03M3/02 ,  H03M3/00 ,  G01R19/00

CPC classification number: G01R13/34 ,  H03K5/24 ,  H03M3/376 ,  H03M3/43

Abstract: A spur-free sigma delta modulator analog-to-digital converter for converting an analog input signal to a digital output signal is provided. A race Josephson junction is provided between the pulse generator and the integrating inductor. The race Josephson junction emits a voltage pulse in response to every sampling pulse. This voltage pulse kills any retained persisting current in the integrating inductor. By adding the race Josephson junction, nonlinearities in the converter are eliminated.A multiple flux quanta feedback generator for creating a multiple digital pulse feedback in response to an input signal is provided. A quantizer connected to the input inductor produces a pulse when the current produced by the input inductor exceeds a predetermined amount. A splitter is connected to the quantizer for producing output pulses. In order to produce 2.sup.n output pulses, 2.sup.n -1 splitters are required. Each of the splitters produces two output pulses in response to a single pulse produced by the quantizer. Each of the 2.sup.n output pulses drives one of 2.sup.n feedback pulse generators. Each of the feedback pulse generators is connected to one of the output pulses to produce 2.sup.n +1 quanta feedback which is fed back to the input inductor.

Abstract translation: 提供了一种用于将模拟输入信号转换为数字输出信号的无差动Σ-Δ调制器模拟 - 数字转换器。 在脉冲发生器和积分电感之间提供一个比赛约瑟夫逊结。 比赛约瑟夫逊结响应于每个采样脉冲发出电压脉冲。 该电压脉冲杀死积分电感器中的任何保留的持续电流。 通过添加比赛约瑟夫逊结，消除了转换器中的非线性。 提供了用于响应于输入信号产生多个数字脉冲反馈的多通量量子反馈发生器。 当输入电感器产生的电流超过预定量时，连接到输入电感器的量化器产生脉冲。 分路器连接到量化器以产生输出脉冲。 为了产生2n个输出脉冲，需要2n-1个分离器。 每个分离器响应于由量化器产生的单个脉冲产生两个输出脉冲。 2n个输出脉冲中的每一个驱动2n个反馈脉冲发生器中的一个。 每个反馈脉冲发生器连接到一个输出脉冲以产生被反馈到输入电感器的2n + 1个量子反馈。

公开(公告)号：US5140324A

公开(公告)日：1992-08-18

申请号：US710856

申请日：1991-06-06

Applicant: John X. Przybysz ,  Donald L. Miller ,  Eric H. Naviasky

Inventor： John X. Przybysz ,  Donald L. Miller ,  Eric H. Naviasky

IPC: H03M3/02

CPC classification number: H03M3/456 ,  H03M3/43

Abstract: A superconducting sigma-delta analog-to-digital converter utilizes a superconducting inductor as the integrator and a Josephson junction connected in series between the inductor and ground as the quantizer. A SQUID generates sampling pulses at a selected GHz frequency which add to the inductor current flowing through the Josephson junction. When the combined current through the Josephson junction exceeds the critical current of the Josephson junction, a voltage pulse is generated which kicks back into the inductor to reduce the inductor current. The voltage across the Josephson junction is, therefore, a one bit digital representation of the analog signal. This one bit digital signal is converted to a multi-bit digital signal preferably by a decimator having superconducting circuits which reduce the frequency of the multi-bit digital signal to a frequency which can be further processed by semiconductor processors. Preferably, a weighting function is utilized in a conversion to improve accuracy.

Abstract translation: 超导Σ-Δ模数转换器利用超导电感器作为积分器，并且将约瑟夫逊结串联连接在电感器和地之间作为量化器。 SQUID以选定的GHz频率产生采样脉冲，这增加了流过约瑟夫逊结的电感电流。 当通过约瑟夫逊结的组合电流超过约瑟夫逊结的临界电流时，产生电压脉冲，其将回到电感器中以减小电感器电流。 因此，约瑟夫逊结上的电压是模拟信号的一位数字表示。 该一比特数字信号优选地被具有超导电路的抽取器转换成多位数字信号，该超导电路将多比特数字信号的频率降低到可由半导体处理器进一步处理的频率。 优选地，在转换中利用加权函数来提高精度。