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    Information processing device, program verification method, and recording medium
    2.
    发明授权
    Information processing device, program verification method, and recording medium 有权
    信息处理装置，程序验证方法和记录介质

    公开(公告)号：US08918654B2

    公开(公告)日：2014-12-23

    申请号：US12274024

    申请日：2008-11-19

    申请人： Mikio Hashimoto ,  Hiroyoshi Haruki ,  Yurie Fujimatsu ,  Takeshi Kawabata

    发明人： Mikio Hashimoto ,  Hiroyoshi Haruki ,  Yurie Fujimatsu ,  Takeshi Kawabata

    IPC分类号： G06F15/16 ,  G06F12/14 ,  G06F21/54

    CPC分类号： G06F12/1416 ,  G06F21/54

    摘要： A first storage unit stores a plurality of security functions each defining a first protection attribute requiring a storage of a value of an argument for input/output of data. A second storage unit stores a program list describing a second protection attribute of a variable indicating a storage area of the data and an executing procedure of a predetermined process. An identifying unit identifies a third protection attribute of an actual argument for input/output of a security function based on the second protection attribute. When a judging unit judges not all of third protection attributes match with first protection attributes, an output unit outputs error information indicating a mismatch of the protection attributes.

    摘要翻译： 第一存储单元存储多个安全功能，每个安全功能定义需要存储数据值以输入/输出数据的第一保护属性。 第二存储单元存储描述指示数据的存储区域的变量的第二保护属性的程序列表和预定处理的执行过程。 识别单元基于第二保护属性识别安全功能的输入/输出的实际参数的第三保护属性。 当判断单元判断不是所有第三保护属性与第一保护属性匹配时，输出单元输出指示保护属性不匹配的错误信息。

    Microprocessor configured to control a process in accordance with a request based on task identification information and the register information identifier
    4.
    发明授权
    Microprocessor configured to control a process in accordance with a request based on task identification information and the register information identifier 失效
    微处理器被配置为根据基于任务识别信息和寄存器信息标识符的请求来控制进程

    公开(公告)号：US08499306B2

    公开(公告)日：2013-07-30

    申请号：US12926251

    申请日：2010-11-04

    申请人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

    发明人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

    IPC分类号： G06F9/46 ,  G06F9/44

    CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/30123 ,  G06F9/485

    摘要： A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.

    摘要翻译： 微处理器执行流水线架构中的程序，其包括任务寄存器管理单元，该任务寄存器管理单元将任务寄存器的值切换到在完成第一任务的执行之后执行第二任务时所使用的第二寄存器信息，如果切换指令 当多个单元执行第一任务时发出第二任务;以及任务管理器，其在将值切换到第二登记信息之后将任务识别信息寄存器的值切换到第二任务标识符，并且授予每个 多个单元允许执行第二任务。

    CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT
    5.
    发明申请
    CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT 审中-公开
    控制设备和计算机程序产品

    公开(公告)号：US20130091372A1

    公开(公告)日：2013-04-11

    申请号：US13622514

    申请日：2012-09-19

    申请人： Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Masaya Tarui ,  Satoshi Shirai ,  Akihiro Shibata

    发明人： Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Masaya Tarui ,  Satoshi Shirai ,  Akihiro Shibata

    IPC分类号： G06F1/30

    CPC分类号： G06F1/32 ,  G06F1/26

    摘要： According to an embodiment, a control device includes a receiving unit, a judging unit, an estimating unit, a deciding unit, a directing unit, and a sending unit. The receiving unit is configured to receive an interrupt request requesting a processing device that includes elements capable of being individually subjected to voltage control to execute an interrupt process. The judging unit is configured to judge a state of the elements. The estimating unit is configured to estimate a start-up time for the element to change into an operating mode after power is supplied. The deciding unit is configured to decide a starting point in time at which power supply is to be started on basis of a difference in the start-up times between the elements. The directing unit is configured to direct a power supply unit for supplying power to the elements. The sending unit is configured to send the interrupt request.

    摘要翻译： 根据实施例，控制装置包括接收单元，判断单元，估计单元，判定单元，引导单元和发送单元。 接收单元被配置为接收请求处理设备的中断请求，该处理设备包括能够单独经受电压控制的元件以执行中断处理。 判断单元被配置为判断元件的状态。 估计单元被配置为在供电之后估计元件变为操作模式的启动时间。 决定单元被配置为基于元件之间的启动时间的差异来确定要开始电源的时间点的起始点。 引导单元被配置为引导供电单元向元件供电。 发送单元配置为发送中断请求。

    Microprocessor
    8.
    发明授权
    Microprocessor 有权
    微处理器

    公开(公告)号：US08191155B2

    公开(公告)日：2012-05-29

    申请号：US11060704

    申请日：2005-02-18

    申请人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

    发明人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

    IPC分类号： H04L29/06

    CPC分类号： G06F11/3648

    摘要： A microprocessor having a processor core includes an information acquisition unit that acquires information encrypted to be used by the processor core, from outside; a decryption unit that decrypts the information with a symmetric key to obtain plain text; and a controller that controls processing on the information acquired by the information acquisition unit based on the symmetric key.

    摘要翻译： 具有处理器核心的微处理器包括信息获取单元，从外部获取加密以供处理器核心使用的信息; 解密单元，用对称密钥解密信息以获得明文; 以及控制器，其基于所述对称密钥来控制对由所述信息获取单元获取的信息的处理。

    Microprocessor
    9.
    发明授权
    Microprocessor 失效
    微处理器

    公开(公告)号：US07707645B2

    公开(公告)日：2010-04-27

    申请号：US11159230

    申请日：2005-06-23

    申请人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

    发明人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

    IPC分类号： G06F7/04 ,  G06F17/30 ,  H04N7/16

    CPC分类号： G06F21/57

    摘要： A microprocessor includes a decryption unit that decrypts information to be utilized by a processor core to obtain plaintext information when the acquired information is encrypted; and a plaintext information storing unit that stores the plaintext information. The microprocessor also includes a protected attribute adding unit that adds a protected attribute indicating one of protection and non-protection to the plaintext information based on whether the decryption has been performed; an access request acquiring unit that acquires an access request to the plaintext information; a request type identifying unit that identifies a type of request of the access request; and an access controlling unit that controls an access to the plaintext information based on the type of request and the protected attribute.

    摘要翻译： 微处理器包括一个解密单元，当所获取的信息被加密时，解密由处理器核心利用的信息以获取明文信息; 以及存储明文信息的明文信息存储单元。 微处理器还包括受保护属性添加单元，该保护属性添加单元基于是否执行了解密，向明文信息添加指示保护和非保护之一的受保护属性; 访问请求获取单元，其获取对所述明文信息的访问请求; 识别访问请求的请求的类型的请求类型识别单元; 以及访问控制单元，其基于请求的类型和所保护的属性来控制对明文信息的访问。

    Control device and computer program product
    10.
    发明授权
    Control device and computer program product 有权
    控制装置和计算机程序产品

    公开(公告)号：US08832335B2

    公开(公告)日：2014-09-09

    申请号：US13334235

    申请日：2011-12-22

    申请人： Akihiro Shibata ,  Koichi Fujisaki ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki

    发明人： Akihiro Shibata ,  Koichi Fujisaki ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki

    IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F1/32 ,  G06F9/48

    CPC分类号： G06F1/3243 ,  G06F9/4812 ,  Y02D10/152 ,  Y02D10/24

    摘要： According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied.

    摘要翻译： 根据实施例，控制装置包括：接收单元，被配置为接收请求由执行一个或多个处理的处理装置执行的中断处理的中断请求; 存储单元，被配置为在其中存储中断请求; 确定单元，被配置为确定所述处理装置的状态; 发送单元，被配置为将所述中断请求发送到所述处理装置; 以及控制单元，被配置为当所述处理设备被所述确定单元确定为处于处理设备未执行所述处理的空闲状态时，将所述接收单元接收到的所述中断请求存储在所述存储单元中，并且预定条件是 并且当满足预定条件时，控制发送单元将存储在存储单元中的中断请求发送到处理装置。