公开(公告)号：US20090303214A1

公开(公告)日：2009-12-10

申请号：US11721926

申请日：2005-12-15

申请人： Hiroyuki Kaigawa

发明人： Hiroyuki Kaigawa

IPC分类号： G09G3/36 ,  H01L21/28 ,  H01L33/00

CPC分类号： G02F1/136286 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1288

摘要： A display control substrate and a method of manufacturing thereof, includes a thin film transistor (TFT) that is provided for each of a multiplicity of pixel sections provided in two dimensions and is an inversely staggered TFT. A gate electrode wiring, a Cs wiring and a source electrode wiring of the TFT are simultaneously formed. An interlayer insulation film is deposited after gate insulation films and semiconductor islands are formed. After contact holes are formed in the interlayer insulation film, at the time of forming a pixel electrode, a connecting portion for connecting cut portions of the source electrode wirings via the contact hole is formed. The source electrode wiring is connected to a source region of the semiconductor island by the connecting portion. This process reduces the number of masks required at the time of manufacturing a TFT substrate, and also reduces the lead time, increases the yield and reduces the manufacturing cost.

摘要翻译： 显示控制基板及其制造方法包括为两维设置的多个像素部分中的每一个设置的并且为交错的TFT的薄膜晶体管（TFT）。 同时形成TFT的栅极布线，Cs布线和源电极布线。 在形成栅绝缘膜和半导体岛之后，沉积层间绝缘膜。 在层间绝缘膜中形成接触孔之后，在形成像素电极时，形成用于经由接触孔连接源电极配线的切断部的连接部。 源电极配线通过连接部与半导体岛的源极区域连接。 该方法减少了在制造TFT基板时所需的掩模数量，并且还减少了提前期，提高了产量并降低了制造成本。

公开(公告)号：US20130037903A1

公开(公告)日：2013-02-14

申请号：US13641443

申请日：2011-04-05

申请人： Hiroyuki Kaigawa ,  Isao Nakanishi

发明人： Hiroyuki Kaigawa ,  Isao Nakanishi

IPC分类号： H01L31/0232

CPC分类号： H01L31/02325

摘要： Disclosed is a display device that is configured such that light that is emitted from a backlight or the like and that illuminates a display panel is prevented from being transmitted through a light-shielding layer that is provided between a light sensor element and a substrate. A liquid crystal display device 1 is provided with: a photodiode 10, which is formed on a substrate 30 that constitutes a part of the display panel; and a light-shielding film 20, which is formed between the substrate 30 and the photodiode 10. The thickness of the light-shielding film 20 is 100 nm or more.

摘要翻译： 公开了一种显示装置，其被配置为使得防止从背光等发射并照亮显示面板的光透过设置在光传感器元件和基板之间的遮光层。 液晶显示装置1设置有：光电二极管10，其形成在构成显示面板的一部分的基板30上; 以及形成在基板30和光电二极管10之间的遮光膜20.遮光膜20的厚度为100nm以上。

公开(公告)号：US20100053114A1

公开(公告)日：2010-03-04

申请号：US12447760

申请日：2007-10-31

申请人： Hiroyuki Kaigawa

发明人： Hiroyuki Kaigawa

IPC分类号： G06F3/041 ,  G03F7/00

CPC分类号： G06F3/044

摘要： A touch panel apparatus includes a position detection electrode formed in a touch region and made of ITO, and a wiring portion provided in a frame region and electrically connected to the position detection electrode. The wiring portion has a first pattern film extended from the position detection electrode and made of ITO, a second pattern film laminated on the first pattern film and made of IZO, and a third pattern film laminated on the second pattern film and made of silver or a silver alloy.

摘要翻译： 触摸面板装置包括形成在触摸区域中并由ITO制成的位置检测电极和设置在框架区域中并电连接到位置检测电极的布线部分。 布线部分具有从位置检测电极延伸并由ITO制成的第一图案膜，层叠在第一图案膜上并由IZO制成的第二图案膜，以及层叠在第二图案膜上并由银制成的第三图案膜 银合金。

公开(公告)号：US20120058589A1

公开(公告)日：2012-03-08

申请号：US13321418

申请日：2010-04-06

申请人： Hiroyuki Kaigawa

发明人： Hiroyuki Kaigawa

IPC分类号： H01L21/336

CPC分类号： H01L31/18 ,  H01L27/1446 ,  H01L27/14683

摘要： Provided is a method of manufacturing a semiconductor device which can form a high-performance photodiode in which variation in output characteristics and performance deterioration are suppressed. A prescribed gate metal is used to form a shield section 34a that covers a portion of a first semiconductor layer 30a for a photodiode that becomes an intrinsic semiconductor region on a gate insulating film 29 and to form first to fourth gate electrodes 34b to 34e that cover portions of respective second to fifth semiconductor layers 30b to 30e for thin film transistors that become channel regions on the gate insulating film 29. Then, using the shield section 34a as a mask, an n-type region and p-type region are formed in the first semiconductor layer 30a. Then, the shield section 34a is removed.

摘要翻译： 提供一种可以形成抑制输出特性和性能劣化的变化的高性能光电二极管的半导体器件的制造方法。 使用规定的栅极金属来形成屏蔽部分34a，该屏蔽部分34a覆盖栅极绝缘膜29上成为本征半导体区域的光电二极管的第一半导体层30a的一部分，并形成第一至第四栅电极34b至34e， 在栅极绝缘膜29上成为沟道区的薄膜晶体管的各个第二至第五半导体层30b至30e的部分。然后，使用屏蔽部分34a作为掩模，形成n型区域和p型区域 第一半导体层30a。 然后，去除屏蔽部分34a。

公开(公告)号：US20110193168A1

公开(公告)日：2011-08-11

申请号：US13125774

申请日：2009-10-22

申请人： Hiroyuki Kaigawa

发明人： Hiroyuki Kaigawa

IPC分类号： H01L27/12 ,  H01L21/8234

CPC分类号： H01L27/1288 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2001/13312 ,  G02F2001/133388 ,  H01L27/0629 ,  H01L27/1214 ,  H01L27/1446 ,  H01L29/78621 ,  H01L29/78627 ,  H01L31/153

摘要： A method for manufacturing a semiconductor device, which includes the steps of: forming a mask layer (20) on a gate insulating film (18), the mask layer (20) having openings over the portions of first and second semiconductor layers that are destined to become low-concentration impurity regions and source and drain regions; forming first conductivity type implantation regions (24b, 24c) in the first and second semiconductor layers respectively by implanting a first conductivity type impurity (22) to the first and second semiconductor layers through the openings in the mask layer (20); forming first and second gate electrodes (26b, 26c) to cover a portion of the first conductivity type implantation regions and portions of the first and second semiconductor layers that are destined to become channel regions; forming another mask layer (28) which has openings over portions of the first conductivity type implantation region (24b) of the first semiconductor layer, said portions being located at both ends of the first semiconductor layer, the entire second semiconductor layer, and a portion of a third semiconductor layer; and implanting the first conductivity type impurity into the first, second, and third semiconductor layers through the openings in the another mask layer (28).

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在栅极绝缘膜（18）上形成掩模层（20），所述掩模层（20）在第一和第二半导体层的部分上具有开口 成为低浓度杂质区和源极和漏极区; 通过在掩模层（20）中的开口将第一和第二半导体层注入第一和第二半导体层，分别在第一和第二半导体层中形成第一导电类型注入区（24b，24c）。 形成第一和第二栅极电极（26b，26c）以覆盖第一导电类型注入区域的一部分和注定成为沟道区域的第一和第二半导体层的部分; 形成在所述第一半导体层的所述第一导电类型注入区域（24b）的部分上具有开口的另一掩模层（28），所述部分位于所述第一半导体层的两端，所述第二半导体层的整个部分 的第三半导体层; 以及通过另一个掩模层（28）中的开口将第一导电类型杂质注入第一，第二和第三半导体层。

公开(公告)号：US20090096759A1

公开(公告)日：2009-04-16

申请号：US12297405

申请日：2007-01-31

申请人： Shogo Nishiwaki ,  Yoshiharu Kataoka ,  Toru Daito ,  Shinya Tanaka ,  Yukihiko Nishiyama ,  Shingo Kawashima ,  Hiroyuki Kaigawa ,  Takayuki Urabe

发明人： Shogo Nishiwaki ,  Yoshiharu Kataoka ,  Toru Daito ,  Shinya Tanaka ,  Yukihiko Nishiyama ,  Shingo Kawashima ,  Hiroyuki Kaigawa ,  Takayuki Urabe

IPC分类号： G06F3/041

CPC分类号： G06F3/0412 ,  G06F3/041 ,  G06F3/044

摘要： A touch panel includes an insulating substrate, a transparent touch electrode provided on the insulating substrate, and a frame portion connected to a periphery of the touch electrode. The touch panel detects a touched position on the touch electrode based on an electric signal through the frame portion. The frame portion is provided between the insulating substrate and the touch electrode.

摘要翻译： 触摸面板包括绝缘基板，设置在绝缘基板上的透明触摸电极和连接到触摸电极周边的框架部分。 触摸面板基于通过框架部分的电信号来检测触摸电极上的触摸位置。 框架部分设置在绝缘基板和触摸电极之间。

公开(公告)号：US20060033855A1

公开(公告)日：2006-02-16

申请号：US11200181

申请日：2005-08-10

申请人： Hiroyuki Kaigawa

发明人： Hiroyuki Kaigawa

IPC分类号： G02F1/136

CPC分类号： H01L27/1259 ,  G02F1/136277 ,  G02F2203/01 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/66772

摘要： A switching element substrate for a liquid crystal display device for transmissive display includes an insulating substrate, and a plurality of switching elements formed on one of surfaces of the insulating substrate. A transmitting region is defined on an exposed part of the other surface of the insulating substrate. Each of the switching elements includes a monocrystalline silicon layer.

摘要翻译： 用于透射显示的液晶显示装置的开关元件基板包括绝缘基板和形成在绝缘基板的一个表面上的多个开关元件。 在绝缘基板的另一表面的露出部分上限定发射区域。 每个开关元件包括单晶硅层。

公开(公告)号：US5506155A

公开(公告)日：1996-04-09

申请号：US184642

申请日：1994-01-21

申请人： Hiroyuki Kaigawa

发明人： Hiroyuki Kaigawa

IPC分类号： H01L21/322 ,  H01L21/306

CPC分类号： H01L21/3221 ,  Y10S148/024

摘要： It is an object of the present invention to provide a method for manufacturing a substrate for a semiconductor device which can increase efficiency of production of the substrate for a semiconductor device, and a method for manufacturing a substrate which can be utilized to produce a highly integrated semiconductor device. A polysilicon layer is formed on both the top surface and the bottom surface of the wafer (see FIG. 4B), before removing the polysilicon layer from the top surface of the wafer (see FIG. 4C). The polysilicon layer which remains on the bottom surface of the wafer is selectively removed, except in the device formation region (see FIG. 4D). Impurities (such as Fe or the like) contained in the wafer are trapped in distortion ST50 and distortion ST60 which occur between the wafer and the polysilicon layer. Since the polysilicon layer is formed separately on the bottom surface of the wafer, the tensile stress of the polysilicon layer is released. As a result, the wafer experiences less curvature, and it is possible to manufacture a substrate for the semiconductor device which can increase efficiency of production.

摘要翻译： 本发明的目的是提供一种半导体装置用基板的制造方法，该半导体装置用基板的制造方法可提高半导体装置的基板的制造效率，以及可用于制造高度集成的基板的制造方法 半导体器件。 在从晶片的顶表面去除多晶硅层之前，在晶片的顶表面和底表面（参见图4B）上形成多晶硅层（见图4C）。 除了在器件形成区域（参见图4D）之外，选择性地除去留在晶片的底表面上的多晶硅层。 包含在晶片中的杂质（例如Fe等）被捕获在晶片和多晶硅层之间发生的变形ST50和变形ST60。 由于多晶硅层分别形成在晶片的底面上，所以多晶硅层的拉伸应力被释放。 结果，晶片经历较少的曲率，并且可以制造可提高生产效率的半导体器件用基板。

公开(公告)号：US08466020B2

公开(公告)日：2013-06-18

申请号：US13321418

申请日：2010-04-06

申请人： Hiroyuki Kaigawa

发明人： Hiroyuki Kaigawa

IPC分类号： H01L21/8234

CPC分类号： H01L31/18 ,  H01L27/1446 ,  H01L27/14683

摘要： Provided is a method of manufacturing a semiconductor device which can form a high-performance photodiode in which variation in output characteristics and performance deterioration are suppressed. A prescribed gate metal is used to form a shield section 34a that covers a portion of a first semiconductor layer 30a for a photodiode that becomes an intrinsic semiconductor region on a gate insulating film 29 and to form first to fourth gate electrodes 34b to 34e that cover portions of respective second to fifth semiconductor layers 30b to 30e for thin film transistors that become channel regions on the gate insulating film 29. Then, using the shield section 34a as a mask, an n-type region and p-type region are formed in the first semiconductor layer 30a. Then, the shield section 34a is removed.

摘要翻译： 提供一种可以形成抑制输出特性和性能劣化的变化的高性能光电二极管的半导体器件的制造方法。 使用规定的栅极金属来形成屏蔽部分34a，该屏蔽部分34a覆盖栅极绝缘膜29上成为本征半导体区域的光电二极管的第一半导体层30a的一部分，并形成第一至第四栅电极34b至34e， 在栅极绝缘膜29上成为沟道区的薄膜晶体管的各个第二至第五半导体层30b至30e的部分。然后，使用屏蔽部分34a作为掩模，形成n型区域和p型区域 第一半导体层30a。 然后，去除屏蔽部分34a。

公开(公告)号：US08421939B2

公开(公告)日：2013-04-16

申请号：US11721926

申请日：2005-12-15

申请人： Hiroyuki Kaigawa

发明人： Hiroyuki Kaigawa

IPC分类号： G02F1/136 ,  G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1288

摘要： A display control substrate and a method of manufacturing thereof, includes a thin film transistor (TFT) that is provided for each of a multiplicity of pixel sections provided in two dimensions and is an inversely staggered TFT. A gate electrode wiring, a Cs wiring and a source electrode wiring of the TFT are simultaneously formed. An interlayer insulation film is deposited after gate insulation films and semiconductor islands are formed. After contact holes are formed in the interlayer insulation film, at the time of forming a pixel electrode, a connecting portion for connecting cut portions of the source electrode wirings via the contact hole is formed. The source electrode wiring is connected to a source region of the semiconductor island by the connecting portion. This process reduces the number of masks required at the time of manufacturing a TFT substrate, and also reduces the lead time, increases the yield and reduces the manufacturing cost.

摘要翻译： 显示控制基板及其制造方法包括为两维设置的多个像素部分中的每一个设置的并且为交错的TFT的薄膜晶体管（TFT）。 同时形成TFT的栅极布线，Cs布线和源电极布线。 在形成栅极绝缘膜和半导体岛之后，沉积层间绝缘膜。 在层间绝缘膜中形成接触孔之后，在形成像素电极时，形成用于经由接触孔连接源电极配线的切断部的连接部。 源电极配线通过连接部与半导体岛的源极区域连接。 该方法减少了在制造TFT基板时所需的掩模数量，并且还减少了提前期，提高了产量并降低了制造成本。