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1.发明授权公开(公告)号：US08319897B2
公开(公告)日：2012-11-27
申请号：US11769309
申请日：2007-06-27
申请人： Seiji Kimura , Masami Ogata , Yosuke Yamamoto , Hisafumi Motoe
发明人： Seiji Kimura , Masami Ogata , Yosuke Yamamoto , Hisafumi Motoe
IPC分类号： H04N5/00
CPC分类号： H04N5/21 , G06T5/002 , G06T5/50 , G06T2207/10016 , H04N5/145
摘要： A noise reduction method for reducing noise in an input video signal to output an output video signal includes the steps of generating a motion-compensated reference video signal from the output video signal; delaying the output video signal to generate a non-motion-compensated reference video signal; mixing the motion-compensated reference video signal with the non-motion-compensated reference video signal to generate a reference video signal; subtracting the generated reference video signal from the input video signal to generate a differential signal; compensating the differential signal to generate a noise reduction signal; and subtracting the noise reduction signal from the input video signal.
摘要翻译： 一种用于降低输入视频信号中的噪声以输出输出视频信号的降噪方法包括以下步骤：从输出视频信号产生运动补偿参考视频信号; 延迟输出视频信号以产生非运动补偿参考视频信号; 将运动补偿参考视频信号与非运动补偿参考视频信号混合以产生参考视频信号; 从输入视频信号中减去生成的参考视频信号以产生差分信号; 补偿差分信号以产生降噪信号; 并从输入视频信号中减去噪声降低信号。
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2.发明授权Signal processing circuit for a moving detection circuit which includes coefficient generator wherein a number of delay devices are connected in series with the first one receiving the output of a moving detection circuit and including a time base filter 失效一种用于移动检测电路的信号处理电路，其包括系数发生器，其中多个延迟器件与接收移动检测电路的输出的第一个串联连接，并且包括时基滤波器
公开(公告)号：US4941046A
公开(公告)日：1990-07-10
申请号：US379055
申请日：1989-07-13
摘要： A signal processing circuit for a moving detection circuit which has a coefficient generator which is connected to an output of a moving detection circuit. A level comparator is connected between the moving detection circuit and the coefficient generator and is also connected to a threshold voltage switch. An isolated-point eliminating circuit is connected between the level comparator and a time base filter which is connected at its output terminal to the input terminal of the coefficient generator. The coefficient generator includes a plurality of one bit delay devices which are connected in series and the plurality of one bit delay devices have a plurality of output terminals, and an adder is connected to the plurality of output terminals so as to add the output signals.
摘要翻译： 一种用于移动检测电路的信号处理电路，其具有连接到移动检测电路的输出的系数发生器。 电平比较器连接在移动检测电路和系数发生器之间，并且还连接到阈值电压开关。 隔离点消除电路连接在电平比较器和时基滤波器之间，时基滤波器在其输出端连接到系数发生器的输入端。 系数发生器包括串联连接的多个1位延迟器件，多个1位延迟器件具有多个输出端子，并且加法器连接到多个输出端子以添加输出信号。
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公开(公告)号：US20050280612A1
公开(公告)日：2005-12-22
申请号：US11156663
申请日：2005-06-21
申请人： Yosuke Yamamoto , Hisafumi Motoe , Satoshi Miura , Takeya Meguro
发明人： Yosuke Yamamoto , Hisafumi Motoe , Satoshi Miura , Takeya Meguro
CPC分类号： G09G3/22 , G09G3/2011 , G09G2300/0426 , G09G2300/06 , G09G2310/0221 , G09G2310/027 , G09G2320/02 , G09G2320/0261
摘要： A matrix type display unit includes a plurality of row wires, and a plurality of column wires, and the matrix type display unit includes a scanning signal applying section performing scanning on each frame of image display through sequentially and alternatively applying a scanning signal to each of the plurality of row wires on a line-by-line basis with normal scan timing, and sequentially and alternatively applying the scanning signal again with scan timing delayed for a predetermined period from the normal scan timing after applying the scanning signal, and a modulation signal applying section applying a modulation signal corresponding to each pixel to a pixel on a line to which the scanning signal is applied with the normal scan timing and a pixel on a line to which the scanning signal is applied with the delay scan timing.
摘要翻译： 矩阵型显示单元包括多个行布线和多列列布线，并且矩阵型显示单元包括扫描信号施加部分，其通过顺序地交替地对每个图像显示帧进行扫描，并且交替地将扫描信号施加到 多条行配线以正常的扫描定时逐行地依次交替地施加扫描信号，并且在施加了扫描信号之后从正常扫描定时延迟预定时间段的扫描定时再次施加扫描信号，以及调制信号 施加部分，将与每个像素对应的调制信号与正常扫描定时施加扫描信号的行上的像素以及以延迟扫描定时施加扫描信号的行上的像素。
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4.发明授权
公开(公告)号：US5021870A
公开(公告)日：1991-06-04
申请号：US379943
申请日：1989-07-14
CPC分类号： H04N7/012
摘要： Interpolated scan lines are produced in response to received video signals which are comprised of conventional interlaced scan lines constituting successive fields. A delay circuit, preferably formed of field memory devices, such as three cascaded field memories, functions to delay the received video signals to provide a first scanned line signal in a given field, the next succeeding scan line signal in that field, an interlaced scan line signal in the next succeeding field and an interlaced scan line signal in the next preceding field. A first combining circuit combines the signal values of the next succeeding field interlaced scan line signal and the next preceding field interlaced scan line signal to form a first combined scan line signal. A second combining circuit combines the signal values of the first scan line signal in the given field and the next succeeding scan line signal in that field to form a second combined scan line signal. The first and second combined scan line signals are level adjusted and added to produce an interpolated scan line signal intermediate successive main scan lines in the given field.
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公开(公告)号：US4673983A
公开(公告)日：1987-06-16
申请号：US915397
申请日：1986-10-06
CPC分类号： H04N5/45
摘要： In a picture-in-picture television receiver, the subpicture signal is A-D converted; the converted digital subpicture signal is latched in response a subpicture clock in synchronism with a subpicture synchronizing signal; the latched signal is latched again and stored in an image memory in response to a main picture synchronizing signal; and the latched signal is read from the image memory in synchronism with the main picture synchronizing signal, in order that the subpicture can stably be inserted in a predetermined area of the main picture by eliminating the unstable data duration during which variation in the subpicture signal is different for each bit signal thereof.
摘要翻译： 在画中画电视接收机中，子画面信号被A-D转换; 经转换的数字子画面信号与子画面同步信号同步地响应于子画面时钟被锁存; 锁存信号被再次锁存并响应于主图像同步信号而存储在图像存储器中; 并且与主画面同步信号同步地从图像存储器中读取锁存信号，以便通过消除子图像信号变化的不稳定数据持续时间，子画面可以稳定地插入主画面的预定区域 对于其每个位信号而言是不同的。
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6.发明授权公开(公告)号：US07092034B2
公开(公告)日：2006-08-15
申请号：US10482675
申请日：2003-04-28
IPC分类号： H04N5/46
摘要： The present invention is related to a video signal processing apparatus and method, a recording medium, and a program which are suitably for use in determining whether an input video signal is standard or nonstandard. In synchronization with the edge of an advance vertical sync signal xAVD, a free-running vertical sync edge counter 31 increments by 1 the count value which cycles between 0 through 7 and outputs the count value to a free-running field ID edge counter 32 and a comparator 33. In synchronization with the rising and falling edges of a field ID signal AFD, the free-running field ID edge counter 32 increments the count value by 1. The comparator 33 generates a nonstandard signal detection signal in correspondence with the FD edge count value with the V count value being 7 and a vertical sync signal xVD being at L level. The present invention is applicable to TV receivers for example.
摘要翻译： 本发明涉及适用于确定输入视频信号是标准还是不标准的视频信号处理装置和方法，记录介质和程序。 与前进垂直同步信号xAVD的边沿同步，自由运行的垂直同步边缘计数器31将从0到7之间循环的计数值递增1，并将计数值输出到自由运行的场ID边缘计数器32， 比较器33。 与场ID信号AFD的上升沿和下降沿同步，自由运行场ID边缘计数器32将计数值递增1.比较器33根据FD边缘计数值生成与FD边缘计数值对应的非标准信号检测信号， V计数值为7，垂直同步信号xVD为L电平。 本发明例如适用于TV接收机。
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公开(公告)号：US20060017663A1
公开(公告)日：2006-01-26
申请号：US11136758
申请日：2005-05-25
申请人： Yosuke Yamamoto , Hisafumi Motoe , Satoshi Miura , Takeya Meguro
发明人： Yosuke Yamamoto , Hisafumi Motoe , Satoshi Miura , Takeya Meguro
IPC分类号： G09G3/20
CPC分类号： G09G3/22 , G09G2310/0205 , G09G2310/0221 , G09G2310/0275 , G09G2320/02 , G09G2320/0261
摘要： A flat display panel such as an FED panel is provided in which high display luminance is obtained with high picture quality and a simple wiring structure. A display device includes a display panel in which column direction wirings 15 and row direction wirings 16 are formed perpendicularly to each other and the column direction wirings 15 are divided into N sets (N is an integer of 2 or more) in the vertical direction of a screen, drive elements 13, 18 which drive each of these N sets of the column direction wirings 15, a scanning element 14 which scans the row direction wirings 16, and an interpolation element 19 which performs flame-interpolation on an input video signal N times; wherein the scanning element 14 simultaneously scans the row direction wirings 16 corresponding to these N sets of the column direction wirings 15 respectively with approximately 1/N the vertical cycle of the video signal, and the drive elements 13, 18, to which an interpolated video signal from the interpolation element 19 is input, drive each of these N sets of the column direction wirings 15 by the interpolated video signal with a frame shifted by 1/N the vertical cycle of the input video signal.
摘要翻译： 提供了诸如FED面板的平面显示面板，其中获得具有高图像质量和简单布线结构的高显示亮度。 显示装置包括：列方向布线15和行方向布线16彼此垂直形成的显示面板，列方向布线15在垂直方向分成N组（N为2以上的整数） 屏幕，驱动这些N组列方向布线15中的每一个的驱动元件13,18，扫描行方向布线16的扫描元件14以及对输入视频信号N进行火焰插值的插值元件19 次 其中扫描元件14同时扫描与这些N组列方向布线15相对应的行方向布线16，其中大约是视频信号的垂直周期的1 / N，以及驱动元件13,18，内插视频 来自插值元件19的信号被输入，通过内插视频信号驱动这些N组列方向布线15中的每一个，并以输入视频信号的垂直周期移位1 / N的帧。
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公开(公告)号：US4985701A
公开(公告)日：1991-01-15
申请号：US379107
申请日：1989-07-13
IPC分类号： G06F5/00 , G06T9/00 , H03M7/30 , H04N7/01 , H04N11/04 , H04N11/20 , H04N19/00 , H04N19/426 , H04N19/51 , H04N19/59 , H04N19/85
CPC分类号： H03M7/30
摘要： A time-division bit number circuit that comprises a bit number expansion system and/or a bit number reduction system. The bit number expansion system converts an N bits signal to a 2N bits signal, while the bit number reduction system converts the 2N bits signal to the N bits signal where N is an integer. Thus, according to the time-division bit amount circuit, the number of memory can be saved, the area of circuit can be reduced and the pattern area of substrate can be reduced.
摘要翻译： 一种包括位数扩展系统和/或比特数减少系统的时分比特数电路。 位数扩展系统将N位信号转换为2N位信号，而位数减少系统将2N位信号转换为N位信号，其中N是整数。 因此，根据时分比特量电路，可以节省存储器的数量，可以减少电路的面积，并且可以减小衬底的图案区域。
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9.发明授权Adaptive comb filter circuit including a plurality of filters and a switching means which results in improved movement detection in television signals 失效包括多个滤波器的自适应梳状滤波器电路和导致电视信号中的运动检测改善的开关装置
公开(公告)号：US4972259A
公开(公告)日：1990-11-20
申请号：US379054
申请日：1989-07-13
IPC分类号： H04N5/14
CPC分类号： H04N5/144
摘要： A moving detection circuit which has a difference level generator which includes at least a frame delay circuit, and a vertical correlation detector which is connected to the difference signal generator and including a plurality of filters connected to the difference signal generator. A switching circuit for selecting one of the plurality of filters is provided and a control circuit is connected to the vertical correlation detector so as to control the switching circuit in response to the output level of the vertical correlation detector.
摘要翻译： 一种移动检测电路，其具有至少包括帧延迟电路的差分电平发生器和连接到差分信号发生器并包括连接到差分信号发生器的多个滤波器的垂直相关检测器。 提供了用于选择多个滤波器之一的开关电路，并且控制电路连接到垂直相关检测器，以响应于垂直相关检测器的输出电平来控制开关电路。
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10.发明申请公开(公告)号：US20080002063A1
公开(公告)日：2008-01-03
申请号：US11769309
申请日：2007-06-27
申请人： Seiji KIMURA , Masami Ogata , Yosuke Yamamoto , Hisafumi Motoe
发明人： Seiji KIMURA , Masami Ogata , Yosuke Yamamoto , Hisafumi Motoe
IPC分类号： H04N5/00
CPC分类号： H04N5/21 , G06T5/002 , G06T5/50 , G06T2207/10016 , H04N5/145
摘要： A noise reduction method for reducing noise in an input video signal to output an output video signal includes the steps of generating a motion-compensated reference video signal from the output video signal; delaying the output video signal to generate a non-motion-compensated reference video signal; mixing the motion-compensated reference video signal with the non-motion-compensated reference video signal to generate a reference video signal; subtracting the generated reference video signal from the input video signal to generate a differential signal; compensating the differential signal to generate a noise reduction signal; and subtracting the noise reduction signal from the input video signal.
摘要翻译： 用于降低输入视频信号中的噪声以输出输出视频信号的降噪方法包括以下步骤：从输出视频信号产生运动补偿参考视频信号; 延迟输出视频信号以生成非运动补偿参考视频信号; 将运动补偿参考视频信号与非运动补偿参考视频信号混合以产生参考视频信号; 从输入视频信号中减去生成的参考视频信号以产生差分信号; 补偿差分信号以产生降噪信号; 并从输入视频信号中减去噪声降低信号。
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