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公开(公告)号：US4673983A
公开(公告)日：1987-06-16
申请号：US915397
申请日：1986-10-06
CPC分类号： H04N5/45
摘要： In a picture-in-picture television receiver, the subpicture signal is A-D converted; the converted digital subpicture signal is latched in response a subpicture clock in synchronism with a subpicture synchronizing signal; the latched signal is latched again and stored in an image memory in response to a main picture synchronizing signal; and the latched signal is read from the image memory in synchronism with the main picture synchronizing signal, in order that the subpicture can stably be inserted in a predetermined area of the main picture by eliminating the unstable data duration during which variation in the subpicture signal is different for each bit signal thereof.
摘要翻译： 在画中画电视接收机中，子画面信号被A-D转换; 经转换的数字子画面信号与子画面同步信号同步地响应于子画面时钟被锁存; 锁存信号被再次锁存并响应于主图像同步信号而存储在图像存储器中; 并且与主画面同步信号同步地从图像存储器中读取锁存信号，以便通过消除子图像信号变化的不稳定数据持续时间，子画面可以稳定地插入主画面的预定区域 对于其每个位信号而言是不同的。
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公开(公告)号：US4985701A
公开(公告)日：1991-01-15
申请号：US379107
申请日：1989-07-13
IPC分类号： G06F5/00 , G06T9/00 , H03M7/30 , H04N7/01 , H04N11/04 , H04N11/20 , H04N19/00 , H04N19/426 , H04N19/51 , H04N19/59 , H04N19/85
CPC分类号： H03M7/30
摘要： A time-division bit number circuit that comprises a bit number expansion system and/or a bit number reduction system. The bit number expansion system converts an N bits signal to a 2N bits signal, while the bit number reduction system converts the 2N bits signal to the N bits signal where N is an integer. Thus, according to the time-division bit amount circuit, the number of memory can be saved, the area of circuit can be reduced and the pattern area of substrate can be reduced.
摘要翻译： 一种包括位数扩展系统和/或比特数减少系统的时分比特数电路。 位数扩展系统将N位信号转换为2N位信号，而位数减少系统将2N位信号转换为N位信号，其中N是整数。 因此，根据时分比特量电路，可以节省存储器的数量，可以减少电路的面积，并且可以减小衬底的图案区域。
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3.发明授权Adaptive comb filter circuit including a plurality of filters and a switching means which results in improved movement detection in television signals 失效包括多个滤波器的自适应梳状滤波器电路和导致电视信号中的运动检测改善的开关装置
公开(公告)号：US4972259A
公开(公告)日：1990-11-20
申请号：US379054
申请日：1989-07-13
IPC分类号： H04N5/14
CPC分类号： H04N5/144
摘要： A moving detection circuit which has a difference level generator which includes at least a frame delay circuit, and a vertical correlation detector which is connected to the difference signal generator and including a plurality of filters connected to the difference signal generator. A switching circuit for selecting one of the plurality of filters is provided and a control circuit is connected to the vertical correlation detector so as to control the switching circuit in response to the output level of the vertical correlation detector.
摘要翻译： 一种移动检测电路，其具有至少包括帧延迟电路的差分电平发生器和连接到差分信号发生器并包括连接到差分信号发生器的多个滤波器的垂直相关检测器。 提供了用于选择多个滤波器之一的开关电路，并且控制电路连接到垂直相关检测器，以响应于垂直相关检测器的输出电平来控制开关电路。
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4.发明授权Signal processing circuit for a moving detection circuit which includes coefficient generator wherein a number of delay devices are connected in series with the first one receiving the output of a moving detection circuit and including a time base filter 失效一种用于移动检测电路的信号处理电路，其包括系数发生器，其中多个延迟器件与接收移动检测电路的输出的第一个串联连接，并且包括时基滤波器
公开(公告)号：US4941046A
公开(公告)日：1990-07-10
申请号：US379055
申请日：1989-07-13
摘要： A signal processing circuit for a moving detection circuit which has a coefficient generator which is connected to an output of a moving detection circuit. A level comparator is connected between the moving detection circuit and the coefficient generator and is also connected to a threshold voltage switch. An isolated-point eliminating circuit is connected between the level comparator and a time base filter which is connected at its output terminal to the input terminal of the coefficient generator. The coefficient generator includes a plurality of one bit delay devices which are connected in series and the plurality of one bit delay devices have a plurality of output terminals, and an adder is connected to the plurality of output terminals so as to add the output signals.
摘要翻译： 一种用于移动检测电路的信号处理电路，其具有连接到移动检测电路的输出的系数发生器。 电平比较器连接在移动检测电路和系数发生器之间，并且还连接到阈值电压开关。 隔离点消除电路连接在电平比较器和时基滤波器之间，时基滤波器在其输出端连接到系数发生器的输入端。 系数发生器包括串联连接的多个1位延迟器件，多个1位延迟器件具有多个输出端子，并且加法器连接到多个输出端子以添加输出信号。
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5.发明授权
公开(公告)号：US5021870A
公开(公告)日：1991-06-04
申请号：US379943
申请日：1989-07-14
CPC分类号： H04N7/012
摘要： Interpolated scan lines are produced in response to received video signals which are comprised of conventional interlaced scan lines constituting successive fields. A delay circuit, preferably formed of field memory devices, such as three cascaded field memories, functions to delay the received video signals to provide a first scanned line signal in a given field, the next succeeding scan line signal in that field, an interlaced scan line signal in the next succeeding field and an interlaced scan line signal in the next preceding field. A first combining circuit combines the signal values of the next succeeding field interlaced scan line signal and the next preceding field interlaced scan line signal to form a first combined scan line signal. A second combining circuit combines the signal values of the first scan line signal in the given field and the next succeeding scan line signal in that field to form a second combined scan line signal. The first and second combined scan line signals are level adjusted and added to produce an interpolated scan line signal intermediate successive main scan lines in the given field.
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6.发明授权Video signal processing apparatus, video signal processing method and video source determining method 失效视频信号处理装置，视频信号处理方法和视频源确定方法公开(公告)号：US07283174B2
公开(公告)日：2007-10-16
申请号：US10475732
申请日：2002-04-23
申请人： Masaharu Tokuhara , Toshio Sarugaku , Naoki Kaneko , Seiko Imai
发明人： Masaharu Tokuhara , Toshio Sarugaku , Naoki Kaneko , Seiko Imai
CPC分类号： H04N7/0112 , H04N7/012 , Y10S348/911
摘要： There is provided a video signal processing apparatus that makes it possible to realize a favorable display of pictures by increasing the detection accuracy of the video source of an input video signal and by using an appropriate scanning method for an output video signal in accordance with the determined type of video source. The video signal processing apparatus includes video source determining means for determining whether the video source of a video signal is a film source, calculating means for calculating a degree of difference between a picture of a field of the video signal and a picture of a field of a delayed video signal, threshold setting means, comparison means for comparing the degree of difference and a threshold and determining whether the pictures of each field match, and a signal pattern detecting means for detecting a signal pattern of a signal outputted by the comparison means and determining whether the video source is a film source, with the threshold setting means outputting respectively different thresholds in a state where the video source is determined to be a film source and a state where the video source is not determined to be a film source.
摘要翻译： 提供了一种视频信号处理装置，其可以通过增加输入视频信号的视频源的检测精度并根据确定的输出视频信号使用适当的输出视频信号的扫描方法来实现图像的良好显示 视频源的类型 视频信号处理装置包括：视频源确定装置，用于确定视频信号的视频源是否是电影源;计算装置，用于计算视频信号的场的图像与场的图像之间的差异程度; 延迟视频信号，阈值设定装置，用于比较差异度和阈值并确定每个场的图像是否匹配的比较装置，以及用于检测由比较装置输出的信号的信号模式的信号模式检测装置，以及 确定视频源是否是电影源，其中阈值设置装置在视频源被确定为电影源的状态和视频源未被确定为电影源的状态下分别输出不同的阈值。
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7.发明授权Luminance and chrominance signal separation circuit employing comparison of level detected signal with a reference level 失效亮度和色度信号分离电路采用电平检测信号与参考电平进行比较
公开(公告)号：US5426470A
公开(公告)日：1995-06-20
申请号：US126188
申请日：1993-09-24
CPC分类号： H04N9/78
摘要： A luminance and chrominance signal separation circuit in which, when its comparing circuits decide that the level of high-frequency components of a luminance signal is lower than a predetermined level, a switching circuit, controlled by a control circuit, selects and outputs a chrominance signal output from a BPF processing circuit.
摘要翻译： 一种亮度和色度信号分离电路，其中当比较电路判定亮度信号的高频分量的电平低于预定电平时，由控制电路控制的开关电路选择并输出色度信号 从BPF处理电路输出。
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8.发明授权Television receiver for extended definition video signal detects number of scan lines and controls signal processors 失效用于扩展定义的电视接收机视频信号检测扫描线数量和控制信号处理器
公开(公告)号：US5227866A
公开(公告)日：1993-07-13
申请号：US845710
申请日：1992-03-04
摘要： A television receiver for extended definition television carries out scanning line interpolation in a way that eliminates picture shift on the screen and ensures normal display when supplied with a non-standard video signal having a scanning line count of other than 262.5 lines per field. The television receiver includes a scanning line interpolation circuit, a normal video signal detection circuit and a interpolation controller. The scanning line interpolation circuit effects scanning line interpolation using either data in the current field or out-of-field data as per the result of motion detection in the picture. The normal video signal detection circuit distinguishes the normal video signal from other signals by detecting the number of scanning lines involved. The interpolation controller causes the scanning line interpolation circuit to effect scanning line interpolation using only the inside-field data if the supplied signal is a non-standard signal.
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9.发明授权Sampling rate converting system for converting the sampling rate of a video signal 失效用于转换视频信号采样率的采样率转换系统
公开(公告)号：US5475436A
公开(公告)日：1995-12-12
申请号：US302033
申请日：1994-09-09
摘要： A plurality of circuit blocks that output digital signals with different sampling frequencies are connected to data buses in common. One of outputs of the circuit blocks is selected and the output is sent to a sampling rate converter circuit block through the data buses. Each of the circuit blocks has a tri-state buffer at its output stage. With an output enable signal, a desired circuit block can be selected.
摘要翻译： 输出具有不同采样频率的数字信号的多个电路块共同地连接到数据总线。 选择电路块的输出之一，并通过数据总线将输出发送到采样率转换器电路块。 每个电路块在其输出级具有三态缓冲器。 使用输出使能信号，可以选择所需的电路块。
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公开(公告)号：US4996595A
公开(公告)日：1991-02-26
申请号：US419901
申请日：1989-10-11
CPC分类号： H04N5/95 , H04N5/93 , Y10S348/91
摘要： Intermediate vertical synchronizing signals are generated to occur between the vertical synchronizing signals normally included in a conventional video signal. A first counter counts clock signals which are synchronized with the horizontal synchronizing signals normally included in the conventional video signal to provide a count representing the number of clock signals which are present in one-half of a field interval of that conventional video signal. The count provided by the first counter during the second preceding field interval is temporarily stored and compared to a count produced by a second counter which counts the clock signals from the beginning of the field interval. An intermediate vertical synchronizing signal is generated when the count of the second counter is equal to the stored count.
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