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公开(公告)号：US08779581B2
公开(公告)日：2014-07-15
申请号：US13290772
申请日：2011-11-07
IPC分类号： H01L23/36
CPC分类号： H01L21/561 , H01L21/565 , H01L23/4334 , H01L24/97 , H01L2224/48227 , H01L2224/97 , H01L2924/01029 , H01L2924/12042 , H01L2924/181 , H01L2924/3511 , H01L2224/85 , H01L2924/00
摘要： An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
摘要翻译： 制造半导体器件封装的方法的实施例包括散热器矩阵和衬底。 多个半导体器件附着在基板上。 然后，在散热片基板和基板之间形成封装体，其中封装体封装半导体器件。 然后，形成多个第一切割槽，其中第一切割槽延伸穿过散热器矩阵并且部分地延伸到包装主体中。 然后，形成多个第二切割槽，其中第二切割槽延伸穿过基板并通过封装主体延伸到第一切割槽，从而将散热器矩阵和基板分离成多个单独的半导体器件封装。
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2.发明授权Method of forming measuring targets for measuring dimensions of substrate in substrate manufacturing process 有权在基板制造工艺中形成用于测量基板尺寸的测量目标的方法公开(公告)号：US08053175B2
公开(公告)日：2011-11-08
申请号：US12136292
申请日：2008-06-10
申请人： Hsiang-Ming Feng
发明人： Hsiang-Ming Feng
IPC分类号： G03F7/20
CPC分类号： H05K1/0269 , H05K1/116 , H05K3/427 , H05K3/4602 , H05K3/4679 , H05K2201/09536 , H05K2201/0959 , H05K2201/0989
摘要： A method of forming measuring targets for measuring the dimensions of a substrate during a substrate manufacturing process is provided. First, a board having a base layer and a conductive layer is provided, wherein the conductive layer is disposed on a surface of the base layer. Then, at least one through hole is formed in the board as a measuring target for measuring the dimensions of the substrate. Next, a plated via is formed in the through hole as another measuring target for measuring the dimensions of the substrate. Thereafter, a patterned dielectric layer is formed on the board to expose the plated via as a next measuring target for measuring the dimensions of the substrate. In the present invention, measuring targets are formed during a substrate manufacturing process and the dimensions of the substrate are measured instantly. The accuracy in process alignment is improved without increasing the fabrication cost.
摘要翻译： 提供了一种在基板制造过程中形成用于测量基板的尺寸的测量目标的方法。 首先，提供具有基底层和导电层的基板，其中导电层设置在基底层的表面上。 然后，在板中形成至少一个通孔作为测量基板尺寸的测量对象。 接下来，在通孔中形成电镀通孔作为用于测量基板的尺寸的另一测量对象。 此后，在板上形成图形化的电介质层，以暴露电镀通孔，作为测量基板尺寸的下一个测量对象。 在本发明中，在基板制造工序中形成测量对象，并且立即测量基板的尺寸。 在不增加制造成本的情况下，改进了工艺对准的精度。
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3.发明申请METHOD OF FORMING MEASURING TARGETS FOR MEASURING DIMENSIONS OF SUBSTRATE IN SUBSTRATE MANUFACTURING PROCESS 有权形成测量靶材的方法，用于测量基板制造工艺中的基板尺寸公开(公告)号：US20090258320A1
公开(公告)日：2009-10-15
申请号：US12136292
申请日：2008-06-10
申请人： Hsiang-Ming Feng
发明人： Hsiang-Ming Feng
IPC分类号： G03F7/20
CPC分类号： H05K1/0269 , H05K1/116 , H05K3/427 , H05K3/4602 , H05K3/4679 , H05K2201/09536 , H05K2201/0959 , H05K2201/0989
摘要： A method of forming measuring targets for measuring the dimensions of a substrate during a substrate manufacturing process is provided. First, a board having a base layer and a conductive layer is provided, wherein the conductive layer is disposed on a surface of the base layer. Then, at least one through hole is formed in the board as a measuring target for measuring the dimensions of the substrate. Next, a plated via is formed in the through hole as another measuring target for measuring the dimensions of the substrate. Thereafter, a patterned dielectric layer is formed on the board to expose the plated via as a next measuring target for measuring the dimensions of the substrate. In the present invention, measuring targets are formed during a substrate manufacturing process and the dimensions of the substrate are measured instantly. The accuracy in process alignment is improved without increasing the fabrication cost.
摘要翻译： 提供了一种在基板制造过程中形成用于测量基板的尺寸的测量目标的方法。 首先，提供具有基底层和导电层的基板，其中导电层设置在基底层的表面上。 然后，在板中形成至少一个通孔作为测量基板尺寸的测量对象。 接下来，在通孔中形成电镀通孔作为用于测量基板的尺寸的另一测量对象。 此后，在板上形成图形化的电介质层，以暴露电镀通孔，作为测量基板尺寸的下一个测量对象。 在本发明中，在基板制造工序中形成测量对象，并且立即测量基板的尺寸。 在不增加制造成本的情况下，改进了工艺对准的精度。
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公开(公告)号：US20120112338A1
公开(公告)日：2012-05-10
申请号：US13290772
申请日：2011-11-07
CPC分类号： H01L21/561 , H01L21/565 , H01L23/4334 , H01L24/97 , H01L2224/48227 , H01L2224/97 , H01L2924/01029 , H01L2924/12042 , H01L2924/181 , H01L2924/3511 , H01L2224/85 , H01L2924/00
摘要： An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
摘要翻译： 制造半导体器件封装的方法的实施例包括散热器矩阵和衬底。 多个半导体器件附着在基板上。 然后，在散热片基板和基板之间形成封装体，其中封装体封装半导体器件。 然后，形成多个第一切割槽，其中第一切割槽延伸穿过散热器矩阵并且部分地延伸到包装主体中。 然后，形成多个第二切割槽，其中第二切割槽延伸穿过基板并通过封装主体延伸到第一切割槽，从而将散热器矩阵和基板分离成多个单独的半导体器件封装。
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5.发明授权公开(公告)号：US08592962B2
公开(公告)日：2013-11-26
申请号：US13219981
申请日：2011-08-29
IPC分类号： H01L23/495
CPC分类号： H01L21/568 , H01L23/3107 , H01L23/49548 , H01L23/49558 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.
摘要翻译： Quad Flat No Leads（QFN）封装包括引线框架，芯片，密封剂和保护层。 引线框架包括多个引线。 每个引线具有被分成接触区域和非接触区域的下表面。 芯片配置在引线框架上并电连接到引线框架。 密封剂封装芯片和引线并填充引线之间的空间。 引线的接触区域和非接触区域被密封剂暴露出来。 保护层覆盖引线的非接触区域。
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6.发明申请公开(公告)号：US20120104584A1
公开(公告)日：2012-05-03
申请号：US13219981
申请日：2011-08-29
IPC分类号： H01L23/495 , H01L21/56
CPC分类号： H01L21/568 , H01L23/3107 , H01L23/49548 , H01L23/49558 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.
摘要翻译： Quad Flat No Leads（QFN）封装包括引线框架，芯片，密封剂和保护层。 引线框架包括多个引线。 每个引线具有被分成接触区域和非接触区域的下表面。 芯片配置在引线框架上并电连接到引线框架。 密封剂封装芯片和引线并填充引线之间的空间。 引线的接触区域和非接触区域被密封剂暴露出来。 保护层覆盖引线的非接触区域。
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