公开(公告)号：US20080126593A1

公开(公告)日：2008-05-29

申请号：US11483622

申请日：2006-07-11

申请人： Hsuan-Yi Wang ,  Hsien-Chung Chen

发明人： Hsuan-Yi Wang ,  Hsien-Chung Chen

IPC分类号： G06F3/00

CPC分类号： G06F13/385 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： An expansion module for a USB port of the present invention is applied to a host system device having a program control unit. The expansion module for a USB port includes a plurality of USB interface linking units, a switching unit, and a power switching unit. The USB interface linking units are individually linked with a peripheral device and output a detecting signal to the program control unit. The switching unit switches the peripheral devices according to a first control signal outputted from the program control unit. The power switching unit turns the power on or off as required for the peripheral devices according to a second control signal outputted from the program control unit. Thereby, the switching unit is switched to make the host system device having a single USB port be linked to a plurality of peripheral devices, and the USB port is expanded.

摘要翻译： 本发明的用于USB端口的扩展模块被应用于具有程序控制单元的主机系统设备。 用于USB端口的扩展模块包括多个USB接口链接单元，切换单元和电源切换单元。 USB接口链接单元与外围设备单独链接，并向程序控制单元输出检测信号。 切换单元根据从程序控制单元输出的第一控制信号切换外围设备。 电源开关单元根据从程序控制单元输出的第二控制信号，按照外围设备的要求开启或关闭电源。 由此，切换单元被切换成使具有单个USB端口的主机系统设备链接到多个外围设备，并且USB端口被扩展。

公开(公告)号：US06484281B1

公开(公告)日：2002-11-19

申请号：US09459763

申请日：1999-12-13

申请人： Hsuan-Yi Wang ,  Jiin Lai ,  Nai-Shung Chang

发明人： Hsuan-Yi Wang ,  Jiin Lai ,  Nai-Shung Chang

IPC分类号： G01R3128

CPC分类号： G01R31/318342

摘要： A software-based simulation system is provided, which can provide the combined functionality of a South Bridge test module and a North Bridge test module based solely on either one of the two modules, i.e., either the South Bridge test module or the North Bridge test module without having to use both. This software-based simulation system is characterized in the use of a PCI master modeling circuit and a PCI slave modeling circuit which are capable of simulating the functionality of the North Bridge chipset in the case that only the South Bridge chipset and no North Bridge chipset is included in the simulation system, and are further capable of simulating the functionality of the South Bridge chipset in the case that only the North Bridge chipset and no South Bridge chipset is included in the simulation system.

摘要翻译： 提供了一个基于软件的仿真系统，可以提供南桥测试模块和北桥测试模块的组合功能，该模块仅基于两个模块之一，即南桥测试模块或北桥测试 模块，而不必使用两者。 该基于软件的仿真系统的特征在于使用PCI主建模电路和PCI从属建模电路，其能够模拟北桥芯片组的功能，仅在南桥芯片组和北桥芯片组为 包括在仿真系统中，并且在模拟系统中仅包括北桥芯片组且没有南桥芯片组的情况下，还能够模拟南桥芯片组的功能。

公开(公告)号：US06738956B2

公开(公告)日：2004-05-18

申请号：US10216174

申请日：2002-08-12

申请人： Jiing Lin ,  Hsuan-Yi Wang ,  Chun-Yi Wu ,  Kuang-Yu Tang

发明人： Jiing Lin ,  Hsuan-Yi Wang ,  Chun-Yi Wu ,  Kuang-Yu Tang

IPC分类号： G06F1750

CPC分类号： G01R31/31722 ,  G01R31/31723 ,  G01R31/3187

摘要： The present invention generally relates to a circuit configuration of a chip and, more particularly to a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses in a testing mode. Thus, the testing of the graphic controller is independent of the main controller module. Moreover, the testing requests are transmitted to the graphic controller by using frequency multiplying modes, and at least one multiplexer and at least one latch are used at the memory end, so that the required pin count for testing is lowered in the present invention.

摘要翻译： 本发明一般涉及一种芯片的电路结构，更具体地说，涉及集成有图形控制器的芯片的电路结构以及用于测试这种电路结构的方法，其中在主控制模块中采用测试电路 使得图形控制器在测试模式下直接连接到多个总线。 因此，图形控制器的测试与主控制器模块无关。 此外，通过使用倍频模式将测试请求发送到图形控制器，并且在存储器端使用至少一个多路复用器和至少一个锁存器，从而在本发明中降低了用于测试的所需引脚数。

公开(公告)号：US06934789B2

公开(公告)日：2005-08-23

申请号：US09894684

申请日：2001-06-27

申请人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Hsuan-Yi Wang ,  Chi-Che Tsai

发明人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Hsuan-Yi Wang ,  Chi-Che Tsai

IPC分类号： G06F13/42 ,  G06F13/38

CPC分类号： G06F13/423

摘要： A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a multiplexer, a strobe generator, and a data distributor. The strobe generator utilizes the bus request signal and bus grant signal to transmit a data strobe signal in response to the PCI clock. According to the rising edge and falling edge of the data strobe signal, the data distributor retrieves data according to the data strobe signal. Further, the invention is compatible with the original PCI bus and allows the PCI bus to transmit data with a dual speed.

摘要翻译： 公开了一种用于发送PCI总线的数据的总线数据接口，结构和方法。 总线数据接口包括高位发送缓冲器，低位发送缓冲器，复用器，选通发生器和数据分配器。 选通发生器利用总线请求信号和总线许可信号来响应于PCI时钟发送数据选通信号。 根据数据选通信号的上升沿和下降沿，数据分配器根据数据选通信号检索数据。 此外，本发明与原始PCI总线兼容，并允许PCI总线以双速传输数据。

公开(公告)号：US06463490B1

公开(公告)日：2002-10-08

申请号：US09447724

申请日：1999-11-24

申请人： Hsuan-Yi Wang ,  Sheng-Chang Peng ,  Nai-Shung Chang

发明人： Hsuan-Yi Wang ,  Sheng-Chang Peng ,  Nai-Shung Chang

IPC分类号： G06F1312

CPC分类号： G06F13/423 ,  G06F13/4031

摘要： The invention provides a method of performing data transfers on a PCI bus between a PCI bus master and a selected device. Wherein, there is a request signal and a grant signal on the PCI bus for a read/write transaction, and during the read/write transaction, the request signal and the grant signal are idle. The method comprises the steps of: (a) driving a first ready signal by the PCI bus master; (b) driving a second read signal by the selected device in response to the first ready signal, which initiates the read/write transaction; (c) using the request signal and the grant signal as a data transfer strobe signal during the write and read transaction, respectively, the data transfer strobe signal has a plurality of clocks; and (d) performing the data transfers on rising and falling edges of the clocks of the data transfer strobe signal.

摘要翻译： 本发明提供了一种在PCI总线主机和所选设备之间的PCI总线上执行数据传输的方法。 其中，在PCI总线上存在用于读/写事务的请求信号和授权信号，并且在读/写事务期间，请求信号和授权信号是空闲的。 该方法包括以下步骤：（a）由PCI总线主机驱动第一就绪信号; （b）响应于启动所述读/写交易的所述第一就绪信号，由所选择的设备驱动第二读信号; （c）分别在写入和读取事务期间使用请求信号和授权信号作为数据传输选通信号，数据传输选通信号具有多个时钟; 和（d）在数据传输选通信号的时钟的上升沿和下降沿执行数据传输。