利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.012 秒)

    Quarter-rate clock recovery circuit and clock recovering method using the same
    3.
    发明授权
    Quarter-rate clock recovery circuit and clock recovering method using the same 有权
    四分之一速率时钟恢复电路和使用其的时钟恢复方法

    公开(公告)号：US07580491B2

    公开(公告)日：2009-08-25

    申请号：US11193329

    申请日：2005-08-01

    申请人： Nyun-Tae Kim ,  Ki-Mio Ueda ,  Hwa-Su Koh ,  Dae-Seung Jeong

    发明人： Nyun-Tae Kim ,  Ki-Mio Ueda ,  Hwa-Su Koh ,  Dae-Seung Jeong

    IPC分类号： H04L7/00

    CPC分类号： H03L7/0814 ,  H04L7/0025 ,  H04L7/033

    摘要： A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks. The controller generates the control signals to control the phase interpolation unit based on the signals output from the phase detector.

    摘要翻译： 四分之一速率时钟恢复电路包括时钟发生器，相位插值单元，相位检测器和控制器。 时钟发生器产生具有输入数据的数据速率的四分之一频率的第一至第四时钟，第二，第三和第四时钟分别相对于第一时钟的相位具有90度，180度和270度的相位差 。 相位插值单元基于控制信号对第一至第四时钟进行相位插值，以产生具有输入数据的数据速率的四分之一频率的第五至第八时钟，第五时钟跟踪输入数据的相位， 第六，第七和第八时钟分别相对于第五时钟的相位具有45度，90度和135度的相位差。 相位检测器基于输入数据和第五到第八时钟输出与输入数据和第五至第八时钟之间的相位差相对应的信号。 控制器基于从相位检测器输出的信号产生控制信号以控制相位插值单元。

    Recovery circuits and methods for the same
    4.
    发明授权
    Recovery circuits and methods for the same 有权
    恢复电路和方法相同

    公开(公告)号：US07489743B2

    公开(公告)日：2009-02-10

    申请号：US11179558

    申请日：2005-07-13

    申请人： Hwa Su Koh ,  Ki Mio Ueda ,  Duck Hyun Chang ,  Nyun Tae Kim ,  Dae Seung Jeong

    发明人： Hwa Su Koh ,  Ki Mio Ueda ,  Duck Hyun Chang ,  Nyun Tae Kim ,  Dae Seung Jeong

    IPC分类号： H03D3/18

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H04L7/0025 ,  H04L7/0337

    摘要： A recovery circuit may include a phase detector, a quadrant decision unit, a quadrant controller, a charge pump unit, and a phase interpolator. The phase detector may compare a phase of input data with a phase of a current output clock to generate first up signal and first down signal and the quadrant decision unit may determine the phase location for the current output clock and output quadrant decision signals based on a phase location. The quadrant controller may output a second up signal and a second down signal based on the first up signal and the first down signal and the quadrant decision signals, and the charge pump unit may output a first and second phase control voltage based on the second up signal and the second down signal. The phase interpolator may select clocks from a plurality of clocks based on the quadrant decision signals and output an output clock signal based on the selected clocks.

    摘要翻译： 恢复电路可以包括相位检测器，象限判定单元，象限控制器，电荷泵单元和相位内插器。 相位检测器可以将输入数据的相位与当前输出时钟的相位进行比较，以产生第一上升信号和第一下降信号，并且象限判定单元可以基于一个信号确定当前输出时钟的相位位置和输出象限判定信号 相位。 象限控制器可以基于第一上升信号和第一下降信号和象限判定信号输出第二上升信号和第二下降信号，并且电荷泵单元可以基于第二上升信号输出第一和第二相位控制电压 信号和第二个下降信号。 相位插值器可以基于象限判定信号从多个时钟中选择时钟，并且基于所选择的时钟输出输出时钟信号。

    Quarter-rate clock recovery circuit and clock recovering method using the same
    5.
    发明申请
    Quarter-rate clock recovery circuit and clock recovering method using the same 有权

    公开(公告)号：US20060029160A1

    公开(公告)日：2006-02-09

    申请号：US11193329

    申请日：2005-08-01

    申请人： Nyun-Tae Kim ,  Ki-Mio Ueda ,  Hwa-Su Koh ,  Dae-Seung Jeong

    发明人： Nyun-Tae Kim ,  Ki-Mio Ueda ,  Hwa-Su Koh ,  Dae-Seung Jeong

    IPC分类号： H04L27/22

    CPC分类号： H03L7/0814 ,  H04L7/0025 ,  H04L7/033

    摘要： A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks. The controller generates the control signals to control the phase interpolation unit based on the signals output from the phase detector.