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    SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF
    1.
    发明申请
    SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF 审中-公开
    半导体存储器系统及其访问方法

    公开(公告)号：US20090164710A1

    公开(公告)日：2009-06-25

    申请号：US12340846

    申请日：2008-12-22

    申请人： Jin-Hyeok Choi ,  Duck-Hyun Chang ,  Jun-Jin Kong ,  Dong-Hyuk Chae ,  Seung-Jae Lee ,  Dong-Ku Kang

    发明人： Jin-Hyeok Choi ,  Duck-Hyun Chang ,  Jun-Jin Kong ,  Dong-Hyuk Chae ,  Seung-Jae Lee ,  Dong-Ku Kang

    IPC分类号： G06F12/02 ,  G06F12/00

    CPC分类号： G11C16/20 ,  G11C16/10

    摘要： A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection.

    摘要翻译： 半导体存储器系统及其访问方法。 半导体存储器系统包括非易失性存储器和存储器控制器。 非易失性存储器将监视数据存储在多个存储单元中的一个或多个中。 存储器控制器控制非易失性存储器。 存储器控制器根据检测结果检测监视数据并调整提供给多个存储单元的偏置电压。

    Spread spectrum clock generator and method for generating a spread spectrum clock signal
    2.
    发明授权
    Spread spectrum clock generator and method for generating a spread spectrum clock signal 有权
    扩频时钟发生器和产生扩频时钟信号的方法

    公开(公告)号：US07558311B2

    公开(公告)日：2009-07-07

    申请号：US11205014

    申请日：2005-08-17

    申请人： Jong-shin Shin ,  Duck-hyun Chang ,  Ji-young Kim ,  Myoung-bo Kwak ,  Il-won Seo ,  Jae-Hyun Park ,  Hyun-goo Kim ,  Chi-won Kim

    发明人： Jong-shin Shin ,  Duck-hyun Chang ,  Ji-young Kim ,  Myoung-bo Kwak ,  Il-won Seo ,  Jae-Hyun Park ,  Hyun-goo Kim ,  Chi-won Kim

    IPC分类号： H04B1/00

    CPC分类号： H03L7/18 ,  H03B23/00 ,  H03L7/0891

    摘要： A spread spectrum clock generator (SSCG) and method of generating a spread spectrum clock (SSC) signal, in which the SSCG may include a controller outputting a given modulation voltage signal based on a difference between an average frequency of a first feedback signal and a comparison frequency signal input thereto, or based on comparison in total phase variations between a second feedback signal and the comparison frequency signal, and a sub-system for generating a first control voltage as a function of an input reference frequency signal and a second feedback signal input thereto. An adder may add the first control voltage signal and the modulation voltage signal to generate a second control voltage signal, and a voltage control oscillator (VCO) may generate the SSC signal based on the second control voltage signal.

    摘要翻译： 扩展频谱时钟发生器（SSCG）和产生扩频时钟（SSC）信号的方法，其中，SSCG可以包括控制器，该控制器基于第一反馈信号的平均频率和 或者基于第二反馈信号和比较频率信号之间的总相位变化的比较，以及用于产生作为输入参考频率信号和第二反馈信号的函数的第一控制电压的子系统 输入。 加法器可以添加第一控制电压信号和调制电压信号以产生第二控制电压信号，并且压控振荡器（VCO）可以基于第二控制电压信号产生SSC信号。

    Recovery circuits and methods for the same
    3.
    发明授权
    Recovery circuits and methods for the same 有权
    恢复电路和方法相同

    公开(公告)号：US07489743B2

    公开(公告)日：2009-02-10

    申请号：US11179558

    申请日：2005-07-13

    申请人： Hwa Su Koh ,  Ki Mio Ueda ,  Duck Hyun Chang ,  Nyun Tae Kim ,  Dae Seung Jeong

    发明人： Hwa Su Koh ,  Ki Mio Ueda ,  Duck Hyun Chang ,  Nyun Tae Kim ,  Dae Seung Jeong

    IPC分类号： H03D3/18

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H04L7/0025 ,  H04L7/0337

    摘要： A recovery circuit may include a phase detector, a quadrant decision unit, a quadrant controller, a charge pump unit, and a phase interpolator. The phase detector may compare a phase of input data with a phase of a current output clock to generate first up signal and first down signal and the quadrant decision unit may determine the phase location for the current output clock and output quadrant decision signals based on a phase location. The quadrant controller may output a second up signal and a second down signal based on the first up signal and the first down signal and the quadrant decision signals, and the charge pump unit may output a first and second phase control voltage based on the second up signal and the second down signal. The phase interpolator may select clocks from a plurality of clocks based on the quadrant decision signals and output an output clock signal based on the selected clocks.

    摘要翻译： 恢复电路可以包括相位检测器，象限判定单元，象限控制器，电荷泵单元和相位内插器。 相位检测器可以将输入数据的相位与当前输出时钟的相位进行比较，以产生第一上升信号和第一下降信号，并且象限判定单元可以基于一个信号确定当前输出时钟的相位位置和输出象限判定信号 相位。 象限控制器可以基于第一上升信号和第一下降信号和象限判定信号输出第二上升信号和第二下降信号，并且电荷泵单元可以基于第二上升信号输出第一和第二相位控制电压 信号和第二个下降信号。 相位插值器可以基于象限判定信号从多个时钟中选择时钟，并且基于所选择的时钟输出输出时钟信号。