公开(公告)号：US10290955B2

公开(公告)日：2019-05-14

申请号：US15986841

申请日：2018-05-23

申请人： Young-Hwan Lee

发明人： Young-Hwan Lee ,  Ok-Ja Yoo

IPC分类号： H01R4/2456 ,  H01R4/242 ,  H01R4/2437 ,  H01R4/2441 ,  H01R4/2425

摘要： Provided is a terminal for an electric wire connector including: a central erection piece configured to have cutting portions inclined downward and outward on both sides of its upper portion; a pair of outer erection pieces configured to be spaced apart at a desired interval on both sides of the central erection piece and have cutting portions that are inclined downward on the upper portion; a connector configured to connect the central erection piece and lower portions of the pair of outer erection pieces; an electrical wire entry portion configured to be a space through which the cutting portions face each other and be a path under which the electrical wire enters; and a core wire connector configured to be arranged on the lower portion communicating with the electric wire entry portion and be a space to connect the central erection piece and the outer erection piece.

公开(公告)号：US08522124B2

公开(公告)日：2013-08-27

申请号：US13069834

申请日：2011-03-23

申请人： Yong-June Kim ,  Jun-Jin Kong ,  Young-Hwan Lee ,  Jae-Hong Kim

发明人： Yong-June Kim ,  Jun-Jin Kong ,  Young-Hwan Lee ,  Jae-Hong Kim

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： G06F11/1048

摘要： An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.

摘要翻译： 错误控制编码（ECC）电路包括第一解码器，第二解码器和控制器。 第一解码器接收包括第一奇偶校验和第二奇偶校验的编码数据。 第一解码器通过使用第一奇偶校验将编码数据解码为第一代码。 第二解码器连接到第一解码器。 第二解码器被配置为当第一解码器被去激活时解码编码数据，并且当第一解码器被去激活时使用第二奇偶校验解码第一代码。 控制器向第一解码器和第二解码器发送控制信号以控制第一解码器和第二解码器。

公开(公告)号：US08410701B2

公开(公告)日：2013-04-02

申请号：US12615125

申请日：2009-11-09

申请人： Young Hwan Lee ,  Kwan Soo Jang ,  Chung Hyun Cho

发明人： Young Hwan Lee ,  Kwan Soo Jang ,  Chung Hyun Cho

IPC分类号： H01J7/44

CPC分类号： H05B33/0809 ,  F21K9/23 ,  F21K9/27 ,  F21V23/008 ,  F21Y2107/20 ,  F21Y2115/10 ,  H01R33/942 ,  H05B33/0803

摘要： An illumination apparatus can include an adapter that converts alternating power into driving power, and controls one or more of the color, brightness, chroma, and blinking of a light emitting device; and a light emitting device illumination part detachably and electrically connected to the adapter, containing one or more light emitting devices configured to emit light in accordance with the driving power and control.

摘要翻译： 照明装置可以包括将交替功率转换为驱动功率的适配器，并且控制发光装置的颜色，亮度，色度和闪烁中的一个或多个; 以及发光装置照明部，其可拆卸地电连接到所述适配器，所述发光装置照明部包含被配置为根据所述驱动力和控制发光的一个或多个发光装置。

公开(公告)号：US08360609B2

公开(公告)日：2013-01-29

申请号：US12615170

申请日：2009-11-09

申请人： Young Hwan Lee ,  Kwan Soo Jang ,  Chung Hyun Cho

发明人： Young Hwan Lee ,  Kwan Soo Jang ,  Chung Hyun Cho

IPC分类号： F21S4/00

CPC分类号： F21V19/02 ,  F21K9/278 ,  F21K9/65 ,  F21V14/02 ,  F21V23/008 ,  F21Y2115/10 ,  H05B33/0803 ,  Y02B20/383

摘要： An illumination apparatus includes an adapter configured to be detachably and electrically connected to a socket and configured to convert alternating power into driving power; a light emitting device illumination part including a light emitting device that is configured to be detachably and electrically connected to the adapter and to emit light according to the driving power from the adapter; and an illumination direction controller that controls an illumination direction of the light emitting device.

摘要翻译： 照明装置包括适配器，其被配置为可拆卸地并且电连接到插座并且被配置为将交流电力转换成驱动电力; 发光装置照明部，其包括被配置为可拆卸地并且电连接到适配器并根据来自适配器的驱动力发光的发光装置; 以及照明方向控制器，其控制发光装置的照明方向。

公开(公告)号：US08332734B2

公开(公告)日：2012-12-11

申请号：US11803255

申请日：2007-05-14

申请人： Min-Goo Kim ,  Beong-Jo Kim ,  Se-Hyoung Kim ,  Soon-Jae Choi ,  Young-Hwan Lee

发明人： Min-Goo Kim ,  Beong-Jo Kim ,  Se-Hyoung Kim ,  Soon-Jae Choi ,  Young-Hwan Lee

IPC分类号： H03M13/03 ,  H03M13/00

CPC分类号： H04L1/0041 ,  H03M13/2957 ,  H03M13/2993 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/6513 ,  H03M13/6569 ,  H04L1/0059 ,  H04L1/0066 ,  H04L1/0069 ,  H04L1/08

摘要： A device and method for rate matching channel-encoded symbols in a data communication system. The rate matching device and method can be applied to a data communication system which uses one or both of a non-systematic code (such as a convolutional code or a linear block code) and a systematic code (such as a turbo code). In one aspect, the rate matching device includes a plurality of rate matching blocks, the number of the rate matching blocks being equal to a reciprocal of a coding rate of a channel encoder. The rate matching device can rate match the symbols encoded with a non-systematic code or the symbols encoded with a systematic code, by changing initial parameters including the number of input symbols, the number of output symbols, and the puncturing or repetition pattern determining parameters.

摘要翻译： 用于数据通信系统中用于速率匹配信道编码符号的装置和方法。 速率匹配装置和方法可以应用于使用非系统代码（例如卷积码或线性块码）和系统码（例如turbo码）中的一个或两个的数据通信系统。 一方面，速率匹配装置包括多个速率匹配块，速率匹配块的数量等于信道编码器的编码率的倒数。 速率匹配装置可以通过改变初始参数（包括输入符号数目，输出符号数量，以及打孔或重复模式确定参数）来对匹配用非系统代码编码的符号或用系统代码编码的符号进行速率匹配 。

公开(公告)号：USD639765S1

公开(公告)日：2011-06-14

申请号：US29369189

申请日：2010-09-03

申请人： Young Hwan Lee

设计人： Young Hwan Lee

公开(公告)号：US07738293B2

公开(公告)日：2010-06-15

申请号：US12213944

申请日：2008-06-26

申请人： Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Jong Han Kim ,  Jae Hong Kim ,  Young Hwan Lee ,  Heeseok Eun ,  Seung-Hwan Song

发明人： Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Jong Han Kim ,  Jae Hong Kim ,  Young Hwan Lee ,  Heeseok Eun ,  Seung-Hwan Song

IPC分类号： G11C16/04 ,  G11C29/04

CPC分类号： G11C11/5628 ,  G11C29/00 ,  G11C2216/14

摘要： A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.

摘要翻译： 提供了存储器编程设备和/或方法。 存储器编程装置可以包括数据存储单元，第一计数单元，索引存储单元和/或编程单元。 数据存储单元可以被配置为存储数据页。 第一计数单元可以被配置为通过基于数据页计数包括在至少一个参考阈值电压状态中的单元的数量来生成索引信息。 索引存储单元可以被配置为存储所生成的索引信息。 编程单元可以被配置为将数据页存储在数据存储单元中，并将生成的索引信息存储在索引存储单元中。 第一计数单元可以将生成的索引信息发送到编程单元。 存储器编程装置可以监视存储器单元中阈值电压的分布状态。

公开(公告)号：US20090091991A1

公开(公告)日：2009-04-09

申请号：US12073100

申请日：2008-02-29

申请人： Kyoung Lae Cho ,  Jun Jin Kong ,  Jong Han Kim ,  Seung Hoon Lee ,  Young Hwan Lee ,  Sung-Jae Byun ,  Ju Hee Park

发明人： Kyoung Lae Cho ,  Jun Jin Kong ,  Jong Han Kim ,  Seung Hoon Lee ,  Young Hwan Lee ,  Sung-Jae Byun ,  Ju Hee Park

IPC分类号： G11C7/00

CPC分类号： G11C11/5628 ,  G11C2211/5647

摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus includes a page buffer configured to store first data of the page programming operation, an input control unit configured to determine whether to invert the first data based on a number of bits having a first value and a number of bits having a second value. The input control unit is further configured to invert the first data to generate second data if the number of bits having a first value is greater than the number of bits having a second value and store the second data in the page buffer. The multi-bit programming apparatus further includes a page programming unit configured to program the second data stored in the page buffer in at least one multi-bit cell.

摘要翻译： 提供了多位编程设备和方法。 一种多位编程装置，包括：页缓冲器，被配置为存储页编程操作的第一数据;输入控制单元，被配置为基于具有第一值的比特数和具有多个比特的比特数来确定是否反转第一数据 第二个值。 输入控制单元还被配置为如果具有第一值的比特数大于具有第二值的比特数，并且将第二数据存储在页面缓冲器中，则反转第一数据以产生第二数据。 该多位编程装置还包括：页面编程单元，被配置为在至少一个多位单元中对存储在页缓冲器中的第二数据进行编程。

公开(公告)号：US20080151621A1

公开(公告)日：2008-06-26

申请号：US11802656

申请日：2007-05-24

申请人： Jun Jin Kong ,  Sung Chung Park ,  Dong Ku Kang ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun

发明人： Jun Jin Kong ,  Sung Chung Park ,  Dong Ku Kang ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

摘要： A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

摘要翻译： 多级单元（MLC）存储器件可以包括“a”个m位MLC存储器单元; 编码器，其以k / n的码率对“k”位数据进行编码，以产生编码比特流; 以及信号映射模块，其向MLC存储器单元施加脉冲以便将编码比特流写入MLC存储器单元。 在设备中，'a'和'm'可以是大于或等于2的整数，'k'和'n'可以是大于或等于1的整数，'n'可能大于'k'。 在设备中存储数据的方法可以包括以k / n的码率对'k'位数据进行编码，以产生编码比特流。 从设备读取数据的方法可以包括以n / k的码率对'n'比特的数据进行解码，以产生解码比特流。

公开(公告)号：US20080137414A1

公开(公告)日：2008-06-12

申请号：US11808173

申请日：2007-06-07

申请人： Sung Chung Park ,  Jun Jin Kong ,  Young Hwan Lee ,  Dong Ku Kang

发明人： Sung Chung Park ,  Jun Jin Kong ,  Young Hwan Lee ,  Dong Ku Kang

IPC分类号： G11C7/10

CPC分类号： G11C11/5621 ,  G11C7/1006 ,  G11C29/00

摘要： A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.

摘要翻译： 提供了一种多级单元（MLC）存储器件及其方法。 示例MLC存储器件可以被配置为执行数据操作，并且可以包括MLC存储器单元，执行第一编码功能的第一编码装置，作为编码功能和解码功能之一的第一编码功能，第二编码装置 执行第二编码功能，所述第二编码功能是编码功能和解码功能之一;以及信号模块，被配置为执行指令所述MLC存储器单元存储由所述第二编码装置输出的数据中的至少一个，如果所述第一和第二编码功能 编码功能是编码功能，并且如果第一和第二编码功能是解码功能，则基于从MLC存储器单元检索的数据来生成解映射比特流。