公开(公告)号：US09698066B2

公开(公告)日：2017-07-04

申请号：US15201675

申请日：2016-07-05

申请人： Bo-Ra Lee ,  Jae-Ho Jeong ,  Nam-Gyu Baek ,  Hyo-Seok Woo ,  Hyun-Sook Yoon ,  Kwang-Yong Lee

发明人： Bo-Ra Lee ,  Jae-Ho Jeong ,  Nam-Gyu Baek ,  Hyo-Seok Woo ,  Hyun-Sook Yoon ,  Kwang-Yong Lee

IPC分类号： H01L21/66 ,  H01L29/423 ,  H01L27/1157 ,  H01L23/00

CPC分类号： H01L22/34 ,  H01L23/562 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.

公开(公告)号：US09570446B1

公开(公告)日：2017-02-14

申请号：US14974275

申请日：2015-12-18

申请人： Hyo Seok Woo ,  In Mo Kim ,  Bora Lee ,  Sun Young Kim ,  Hoo Sung Cho

发明人： Hyo Seok Woo ,  In Mo Kim ,  Bora Lee ,  Sun Young Kim ,  Hoo Sung Cho

IPC分类号： H01L23/48 ,  G01R31/28 ,  H01L23/485 ,  G01R1/067 ,  H01L27/105 ,  H01L23/00 ,  H01L23/522 ,  H01L21/66

CPC分类号： H01L22/32 ,  G01R1/067 ,  G01R31/28 ,  G11C5/025 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/5602 ,  H01L22/34 ,  H01L24/09 ,  H01L2224/08055 ,  H01L2224/09055

摘要： A semiconductor device includes a plurality of semiconductor devices, a plurality of metal lines electrically connected to at least one of the semiconductor devices, and a protective layer on the metal lines. The protective layer includes a plurality of open areas partially exposing the metal lines and which serves as pads. A first pad includes a first area that extends from at least one of the metal lines and at least one second area around and separated from the first area.

摘要翻译： 半导体器件包括多个半导体器件，电连接到至少一个半导体器件的多个金属线以及金属线上的保护层。 保护层包括部分地露出金属线并用作垫的多个开放区域。 第一垫包括从金属线中的至少一个延伸的第一区域和围绕第一区域分离的至少一个第二区域。

公开(公告)号：US20170103929A1

公开(公告)日：2017-04-13

申请号：US15201675

申请日：2016-07-05

申请人： Bo-Ra LEE ,  Jae-Ho JEONG ,  Nam-Gyu BAEK ,  Hyo-Seok WOO ,  Hyun-Sook YOON ,  Kwang-Yong LEE

发明人： Bo-Ra LEE ,  Jae-Ho JEONG ,  Nam-Gyu BAEK ,  Hyo-Seok WOO ,  Hyun-Sook YOON ,  Kwang-Yong LEE

IPC分类号： H01L21/66 ,  H01L27/115 ,  H01L23/00 ,  H01L29/423

CPC分类号： H01L22/34 ,  H01L23/562 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.