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公开(公告)号：US20230317657A1
公开(公告)日：2023-10-05
申请号：US17970111
申请日：2022-10-20
发明人： Wonil SEO
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/09 , H01L24/32 , H01L24/48 , H01L24/08 , H01L24/73 , H01L25/0657 , H01L24/85 , H01L2924/1011 , H01L2924/10156 , H01L2924/1436 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06562 , H01L2225/06565 , H01L2224/73265 , H01L2224/48091 , H01L2224/48229 , H01L2224/32145 , H01L2224/0801 , H01L2224/08054 , H01L2224/08055 , H01L2224/0903 , H01L2224/09051 , H01L2224/0951 , H01L2224/09153 , H01L2224/09152 , H01L2224/09179 , H01L2224/85091
摘要： Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises semiconductor chips stacked on a substrate and including first and second pads on top surfaces thereof, and bonding wires connecting the first and second pads to the substrate. The semiconductor chips alternately protrude in a first direction and its opposite direction. The semiconductor chip has a first lateral surface spaced apart from another semiconductor chip. The top surface of the semiconductor chip is provided thereon with a first arrangement line extending along the first lateral surface and with second arrangement lines extending from opposite ends of the first arrangement line. Wherein as a distance between the first and second arrangement lines increases, a distance between the second arrangement lines and the first lateral surface increases. The first pads are arranged along the first arrangement line. The second pads are arranged along the second arrangement lines.
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公开(公告)号：US20230230946A1
公开(公告)日：2023-07-20
申请号：US17939127
申请日：2022-09-07
发明人： Seongyo KIM , UN-BYOUNG KANG , MINSOO KIM , SANG-SICK PARK , Seungyoon JUNG
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/09 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/08 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/81203 , H01L24/81 , H01L2924/3511 , H01L2924/182 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06544 , H01L2225/06589 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/1703 , H01L2224/17055 , H01L2224/17104 , H01L2224/17179 , H01L2224/17132 , H01L2224/16012 , H01L2224/16055 , H01L2224/16059 , H01L2224/16104 , H01L2224/0801 , H01L2224/08056 , H01L2224/08055 , H01L2224/0903 , H01L2224/09179 , H01L2224/09132 , H01L2224/73204
摘要： A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region. Each of the connection terminals may include a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad. The convex portion may protrude in a direction away from a center of the first die. Protruding distances of the convex portions may increase in a direction from the center of the first die toward an outside of the first die.
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公开(公告)号：US20240071976A1
公开(公告)日：2024-02-29
申请号：US17899574
申请日：2022-08-30
发明人： Wei Zhou
IPC分类号： H01L23/00 , H01L23/29 , H01L23/31 , H01L25/065
CPC分类号： H01L24/32 , H01L23/291 , H01L23/3171 , H01L24/08 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/73 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L2224/0801 , H01L2224/08055 , H01L2224/08056 , H01L2224/16014 , H01L2224/16055 , H01L2224/16148 , H01L2224/27622 , H01L2224/29011 , H01L2224/29191 , H01L2224/32013 , H01L2224/32054 , H01L2224/32058 , H01L2224/3207 , H01L2224/32145 , H01L2224/73204 , H01L2224/81203 , H01L2224/81895 , H01L2224/83009 , H01L2224/83099 , H01L2224/83896 , H01L2224/83907 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541
摘要： This document discloses techniques, apparatuses, and systems for a semiconductor device with a polymer layer. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die has a first active side with first circuitry and a first back side opposite the first active side. Contact pads and a layer of polymer material are disposed at the first back side such that the layer of polymer material includes openings that expose the contact pads. The second semiconductor die has second circuitry disposed at a second active side. Interconnect structures are also disposed at the second active side such that the interconnect structures extend into the openings and couple to contact pads. A passivation layer (e.g., dielectric material) is disposed at the second active side and directly bonded to the layer of polymer material to reliably couple the two semiconductor dies.
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公开(公告)号：US20230369178A1
公开(公告)日：2023-11-16
申请号：US18170159
申请日：2023-02-16
发明人： Toshiyuki HATA
IPC分类号： H01L23/495 , H01L23/00 , H01L25/065 , H01L23/498
CPC分类号： H01L23/49513 , H01L24/08 , H01L24/32 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L23/49816 , H01L2924/182 , H01L2224/08055 , H01L2224/08113 , H01L2224/32245 , H01L2224/48245 , H01L2224/4814 , H01L2224/4903
摘要： A package construction includes: a die pad, and a suspension lead remaining portion connected to the die pad. Here, an offset portion is provided from a peripheral edge portion of the die pad to the suspension lead remaining portion. Also, the suspension lead remaining portion has: a first end portion connected to the die pad, and a second end portion opposite the first end portion. Further, the second end portion of the suspension lead remaining portion is exposed from the side surface of the sealing body at a position spaced apart from each of the upper surface and the lower surface.
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公开(公告)号：US12119315B2
公开(公告)日：2024-10-15
申请号：US17650851
申请日：2022-02-13
发明人： Chih-Wei Chang
IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L25/065
CPC分类号： H01L24/05 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L2224/03622 , H01L2224/05009 , H01L2224/05011 , H01L2224/05014 , H01L2224/05015 , H01L2224/05017 , H01L2224/05073 , H01L2224/0801 , H01L2224/08055 , H01L2224/08056 , H01L2224/08059 , H01L2224/0807 , H01L2224/08147 , H01L2224/08148 , H01L2224/80895 , H01L2225/06524 , H01L2225/06544 , H01L2225/06548
摘要： A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.
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公开(公告)号：US20230411327A1
公开(公告)日：2023-12-21
申请号：US18176474
申请日：2023-02-28
申请人： Kioxia Corporation
发明人： Masayoshi TAGAMI
CPC分类号： H01L24/08 , H10B80/00 , H01L24/09 , H01L24/05 , H01L25/16 , H01L2224/05005 , H01L2224/05014 , H01L2224/05018 , H01L2224/05073 , H01L2224/05573 , H01L2224/05541 , H01L2224/05558 , H01L2224/0903 , H01L2224/09051 , H01L2224/0801 , H01L2224/08055 , H01L2224/08057 , H01L2224/08145 , H01L2924/1438 , H01L2924/1431 , H01L2224/05647 , H01L2224/05554
摘要： According to one embodiment, a semiconductor device includes a first chip with a first electrode and a second electrode and a second chip with a third electrode and a fourth electrode. The first and second chips are bonded to each other with the first electrode contacting the third electrode and the second electrode contacting the fourth electrode. A thickness of the first electrode in a first direction perpendicular to a bonding interface between the first chip and the second chip is less than a thickness of the second electrode in the first direction. A planar area of the first electrode at the bonding interface is greater than a planar area of the second electrode at the bonding interface.
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公开(公告)号：US20230378110A1
公开(公告)日：2023-11-23
申请号：US18067773
申请日：2022-12-19
发明人： MINKI KIM , Seungduk Baek , Hyuekjae Lee
CPC分类号： H01L24/08 , H10B80/00 , H01L24/03 , H01L24/05 , H01L24/80 , H01L2924/1438 , H01L2924/1431 , H01L2224/0801 , H01L2224/08056 , H01L2224/08055 , H01L2224/0807 , H01L2224/08059 , H01L2224/08058 , H01L2224/08121 , H01L2224/08145 , H01L2224/08225 , H01L2224/05647 , H01L2224/05687 , H01L2224/80895 , H01L2224/80896 , H01L2224/03831 , H01L2224/0384
摘要： Provided is a semiconductor device including lower and upper structures. The lower structure includes a first substrate, a first pad on the first substrate, and a first insulating layer surrounding the first pad. The upper structure includes a second substrate, a second pad on the second substrate, and a second insulating layer surrounding the second pad. The upper and lower structures contact each other. The first and second pads contact each other. The first and second insulating layers contact each other. The first insulating layer includes a first recess adjacent the first pad, the second insulating layer includes a second recess that is adjacent the second pad and overlaps the first recess, and a cavity is defined by the first recess and the second recess, and particles of a metallic material constituting the first and second pads are in the cavity.
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公开(公告)号：US09570446B1
公开(公告)日：2017-02-14
申请号：US14974275
申请日：2015-12-18
申请人： Hyo Seok Woo , In Mo Kim , Bora Lee , Sun Young Kim , Hoo Sung Cho
发明人： Hyo Seok Woo , In Mo Kim , Bora Lee , Sun Young Kim , Hoo Sung Cho
IPC分类号： H01L23/48 , G01R31/28 , H01L23/485 , G01R1/067 , H01L27/105 , H01L23/00 , H01L23/522 , H01L21/66
CPC分类号： H01L22/32 , G01R1/067 , G01R31/28 , G11C5/025 , G11C29/1201 , G11C29/48 , G11C2029/5602 , H01L22/34 , H01L24/09 , H01L2224/08055 , H01L2224/09055
摘要： A semiconductor device includes a plurality of semiconductor devices, a plurality of metal lines electrically connected to at least one of the semiconductor devices, and a protective layer on the metal lines. The protective layer includes a plurality of open areas partially exposing the metal lines and which serves as pads. A first pad includes a first area that extends from at least one of the metal lines and at least one second area around and separated from the first area.
摘要翻译： 半导体器件包括多个半导体器件，电连接到至少一个半导体器件的多个金属线以及金属线上的保护层。 保护层包括部分地露出金属线并用作垫的多个开放区域。 第一垫包括从金属线中的至少一个延伸的第一区域和围绕第一区域分离的至少一个第二区域。
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公开(公告)号：US20240203855A1
公开(公告)日：2024-06-20
申请号：US18356721
申请日：2023-07-21
发明人： Jaemok JUNG , Un-Byoung KANG , Dowan KIM , Sung Keun PARK , Jongho PARK , Ju-Il CHOI
IPC分类号： H01L23/498 , H01L21/56 , H01L21/768 , H01L23/00 , H01L23/31 , H01L23/48
CPC分类号： H01L23/49827 , H01L21/565 , H01L21/76811 , H01L23/3128 , H01L23/481 , H01L24/08 , H01L24/32 , H01L2224/08055 , H01L2224/08155 , H01L2224/32146 , H01L2224/32235 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/182
摘要： An embodiment provides a semiconductor package including: a first redistribution layer substrate; a semiconductor chip on the first redistribution layer substrate; a coupling member on the first redistribution layer substrate, wherein the coupling member is spaced apart from the semiconductor chip; an encapsulant on the first redistribution layer substrate, the semiconductor chip, and the coupling member; and a second redistribution layer substrate on the encapsulant, wherein the coupling member includes a vertical wire and a metal portion extending around the vertical wire, and wherein a first end of the coupling member is electrically connected to the first redistribution layer substrate, and a second end of the coupling member is electrically connected to the second redistribution layer substrate.
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公开(公告)号：US20230411328A1
公开(公告)日：2023-12-21
申请号：US18060036
申请日：2022-11-30
申请人： Kioxia Corporation
发明人： Shinya ARAI , Yuta TAGUCHI
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/09 , H01L24/08 , H01L25/0657 , H01L2924/1431 , H01L2924/1438 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06593 , H01L2224/08145 , H01L2224/09515 , H01L2924/30205 , H01L2224/08055 , H01L2224/0801 , H01L2224/0903 , H01L2224/09051 , H01L2224/09179 , H01L2224/09132 , H01L2224/09133
摘要： According to an embodiment, a semiconductor device includes a first chip including a substrate, and a second chip bonded to the first chip at a first surface. Each of the first chip and the second chip includes an element region, and an end region including a chip end portion. The first chip includes a plurality of first electrodes that are arranged on the first surface in the end region and are in an electrically uncoupled state. The second chip includes a plurality of second electrodes that are arranged on the first surface in the end region, are in an electrically uncoupled state, and are respectively in contact with the first electrodes.
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