公开(公告)号：US09275904B2

公开(公告)日：2016-03-01

申请号：US12614991

申请日：2009-11-09

Applicant: Sung-Jin Whang ,  Moon-Sig Joo ,  Yong-Seok Eun ,  Kwon Hong ,  Bo-Min Seo ,  Kyoung-Eun Chang ,  Seung-Woo Shin

Inventor： Sung-Jin Whang ,  Moon-Sig Joo ,  Yong-Seok Eun ,  Kwon Hong ,  Bo-Min Seo ,  Kyoung-Eun Chang ,  Seung-Woo Shin

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32139 ,  H01L27/10873 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42376 ,  H01L29/4933

Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.

Abstract translation: 一种制造半导体器件的方法，包括在衬底上形成栅极图案，形成覆盖每个栅极图案的顶部和侧壁的导电层，在导电层上形成用于硅化工艺的金属层，以及硅化导电层和栅极图案 使用金属层。

公开(公告)号：US09019767B2

公开(公告)日：2015-04-28

申请号：US13398397

申请日：2012-02-16

Applicant: Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

Inventor： Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

IPC: G11C16/04 ,  H01L27/115 ,  G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0408 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract translation: 非易失性存储器件包括从衬底垂直延伸的沟道，沿着沟道堆叠的多个存储单元; 连接到所述沟道的第一端部的源极区域和与所述沟道的第二端部连接的位线，其中与所述源极区域相邻的所述沟道的所述第一端部形成为未掺杂的半导体层或半导体 层掺杂有P型杂质。

公开(公告)号：US20130099304A1

公开(公告)日：2013-04-25

申请号：US13603049

申请日：2012-09-04

Applicant: Min Soo KIM ,  Dong Sun Sheen ,  Young Jin Lee ,  Jin Hae Choi ,  Joo Hee Han ,  Sung Jin Whang

Inventor： Min Soo KIM ,  Dong Sun Sheen ,  Young Jin Lee ,  Jin Hae Choi ,  Joo Hee Han ,  Sung Jin Whang

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11582 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/32135 ,  H01L27/11556 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.

公开(公告)号：US20120213009A1

公开(公告)日：2012-08-23

申请号：US13398397

申请日：2012-02-16

Applicant: Seiichi ARITOME ,  Hyun-Seung YOO ,  Sung-Jin WHANG

Inventor： Seiichi ARITOME ,  Hyun-Seung YOO ,  Sung-Jin WHANG

IPC: G11C16/14 ,  H01L29/788

CPC classification number: G11C16/14 ,  G11C16/0408 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract translation: 非易失性存储器件包括从衬底垂直延伸的沟道，沿着沟道堆叠的多个存储单元; 连接到所述沟道的第一端部的源极区域和与所述沟道的第二端部连接的位线，其中与所述源极区域相邻的所述沟道的所述第一端部形成为未掺杂的半导体层或半导体 层掺杂有P型杂质。

公开(公告)号：US09112044B2

公开(公告)日：2015-08-18

申请号：US13315147

申请日：2011-12-08

Applicant: Sung Jin Whang ,  Ki Hong Lee

Inventor： Sung Jin Whang ,  Ki Hong Lee

IPC: H01L27/108 ,  H01L29/788 ,  H01L21/764 ,  H01L27/115 ,  H01L29/792 ,  H01L29/786

CPC classification number: H01L27/1052 ,  H01L21/764 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/7889 ,  H01L29/7926

Abstract: A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.

Abstract translation: 三维（3-D）非易失性存储器件包括并行延伸的多个字线结构，并且包括交替堆叠在衬底上的多个层间电介质层和多个字线，多个通道 从被配置为穿透多个层间电介质层和多个字线的基板突出，以及形成在多个字线结构之间的气隙。

公开(公告)号：US08847300B2

公开(公告)日：2014-09-30

申请号：US12640491

申请日：2009-12-17

Applicant: Sung-Jin Whang ,  Moon-Sig Joo ,  Kwon Hong ,  Jung-Yeon Lim ,  Won-Kyu Kim ,  Bo-Min Seo ,  Kyoung-Eun Chang

Inventor： Sung-Jin Whang ,  Moon-Sig Joo ,  Kwon Hong ,  Jung-Yeon Lim ,  Won-Kyu Kim ,  Bo-Min Seo ,  Kyoung-Eun Chang

IPC: H01L29/76 ,  H01L29/788 ,  H01L27/108 ,  H01L29/423 ,  H01L21/28 ,  H01L23/00 ,  H01L21/321 ,  H01L29/41

CPC classification number: H01L21/28518 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/321 ,  H01L21/7685 ,  H01L24/02 ,  H01L27/10873 ,  H01L29/413 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/12032 ,  H01L2924/00

Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.

Abstract translation: 一种半导体器件，包括导电层，形成在导电层上的扩散阻挡层，包括难熔金属化合物，并在表面处理之后获得，以及形成在扩散阻挡层上的金属硅化物层。 通过表面处理增加扩散阻挡层的表面能，可以改善扩散阻挡层和金属硅化物层之间的粘合性。 因此，尽管金属硅化物层在高温工艺中熔合，但是可以防止在扩散阻挡层和金属硅化物层之间的界面处产生空隙。 此外，通过表面处理增加导电层的表面能，可以增加导电层与扩散阻挡层之间的粘合性。

公开(公告)号：US08735962B2

公开(公告)日：2014-05-27

申请号：US13599680

申请日：2012-08-30

Applicant: Sung Jin Whang ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Min Soo Kim

Inventor： Sung Jin Whang ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Min Soo Kim

IPC: H01L29/788 ,  H01L21/20

CPC classification number: H01L27/11556 ,  H01L29/7889

Abstract: A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.

Abstract translation: 根据本发明的实施例的半导体器件包括从半导体衬底向上突出的垂直沟道层，覆盖垂直沟道层的侧壁的隧道绝缘层，彼此分离并堆叠的多个浮动栅极 沿着垂直沟道层，并且在其间插入隧道绝缘层的周围的垂直沟道层，分别包围多个浮置栅极的多个控制栅极和设置在多个控制栅极之间的层间绝缘层。

公开(公告)号：US08711630B2

公开(公告)日：2014-04-29

申请号：US13334423

申请日：2011-12-22

Applicant: Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

Inventor： Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

IPC: G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  H01L27/11556

Abstract: A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and two neighboring memory cells share one control gate. The programming method includes applying a first program voltage to a first control gate of a selected memory cell and a second program voltage that is higher than the first program voltage to a second control gate of the selected memory cell, and applying a first pass voltage to a third control gate disposed adjacent to the first control gate and a second pass voltage that is lower than the first pass voltage to a fourth control gate disposed adjacent to the second control gate.

Abstract translation: 一种非易失性存储器件的编程方法，包括具有多个浮动栅极和多个控制栅极交替布置的存储器单元串，其中每个存储器单元包括一个浮置栅极和两个控制栅极， 浮动门和两个相邻的存储单元共享一个控制门。 编程方法包括将第一编程电压施加到所选择的存储单元的第一控制栅极，以及将高于第一编程电压的第二编程电压施加到所选存储单元的第二控制栅极，并将第一通过电压施加到 与第一控制栅极相邻设置的第三控制栅极和与第二控制栅极相邻设置的第四控制栅极低于第一通过电压的第二通过电压。

公开(公告)号：US20130168752A1

公开(公告)日：2013-07-04

申请号：US13604073

申请日：2012-09-05

Applicant: Min-Soo KIM ,  Dong-Sun SHEEN ,  Seung-Ho PYI ,  Sung-Jin WHANG

Inventor： Min-Soo KIM ,  Dong-Sun SHEEN ,  Seung-Ho PYI ,  Sung-Jin WHANG

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L27/11582

Abstract: A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.

Abstract translation: 非易失性存储器件包括：衬底，其包括表面，形成在所述衬底的表面上的从所述表面垂直突出的沟道层，以及沿所述沟道层交替堆叠的多个层间电介质层和多个栅极电极层， 其中所述多个栅极电极层从所述多个层间电介质层突出。

公开(公告)号：US20130049095A1

公开(公告)日：2013-02-28

申请号：US13599680

申请日：2012-08-30

Applicant: Sung Jin WHANG ,  Dong Sun SHEEN ,  Seung Ho PYI ,  Min Soo KIM

Inventor： Sung Jin WHANG ,  Dong Sun SHEEN ,  Seung Ho PYI ,  Min Soo KIM

IPC: H01L29/788 ,  H01L21/20

CPC classification number: H01L27/11556 ,  H01L29/7889

Abstract: A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.

Abstract translation: 根据本发明的实施例的半导体器件包括从半导体衬底向上突出的垂直沟道层，覆盖垂直沟道层的侧壁的隧道绝缘层，彼此分离并堆叠的多个浮动栅极 沿着垂直沟道层，并且在其间插入隧道绝缘层的周围的垂直沟道层，分别包围多个浮置栅极的多个控制栅极和设置在多个控制栅极之间的层间绝缘层。