公开(公告)号：US08675404B2

公开(公告)日：2014-03-18

申请号：US13475204

申请日：2012-05-18

申请人： Hyun-Seung Yoo ,  Sung-Joo Hong ,  Seiichi Aritome ,  Seok-Kiu Lee ,  Sung-Kye Park ,  Gyu-Seog Cho ,  Eun-Seok Choi ,  Han-Soo Joo

发明人： Hyun-Seung Yoo ,  Sung-Joo Hong ,  Seiichi Aritome ,  Seok-Kiu Lee ,  Sung-Kye Park ,  Gyu-Seog Cho ,  Eun-Seok Choi ,  Han-Soo Joo

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

摘要翻译： 一种非易失性存储器件的读取方法，包括分别包括一个浮动栅极和两个控制栅极的多个存储器单元，两个控制栅极分别与浮置栅极的两个交替侧相邻设置，并且两个相邻的存储单元共享一个 所述读取方法包括将读取电压施加到所选择的存储器单元的控制栅极，将第二通过电压施加到与所选择的存储器单元的控制栅极不同的存储单元的控制栅极的替代控制栅极，所述存储器单元从控制栅极开始， 所选择的存储单元，以及施加低于第二通过电压的第一通过电压，以从控制栅极开始的第二选择的存储单元开始，将不同于所选存储单元的控制栅极的存储单元的控制栅极交替 。

公开(公告)号：US08482055B2

公开(公告)日：2013-07-09

申请号：US13304901

申请日：2011-11-28

申请人： Eun-Seok Choi ,  Hyun-Seung Yoo

发明人： Eun-Seok Choi ,  Hyun-Seung Yoo

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L28/20

摘要： A non-volatile memory device includes a substrate including a resistor layer having a resistance lower than that of a source line, channel structures including a plurality of inter-layer dielectric layers that are alternately staked with a plurality of channel layers over the substrate, and the source line configured to contact sidewalls of the channel layers, where a lower end of the source line contacts the resistor layer.

摘要翻译： 非易失性存储器件包括：衬底，其具有电阻低于源极线的电阻层，沟道结构包括多个层间电介质层，所述多个层间电介质层与衬底上的多个沟道层交替地淀积;以及 源极线被配置为接触沟道层的侧壁，其中源极线的下端接触电阻层。

公开(公告)号：US20110199813A1

公开(公告)日：2011-08-18

申请号：US12980983

申请日：2010-12-29

申请人： Hyun-Seung Yoo ,  Eun-Seok Choi

发明人： Hyun-Seung Yoo ,  Eun-Seok Choi

IPC分类号： G11C11/00 ,  H01L21/8242

CPC分类号： H01L27/249 ,  G11C5/02 ,  G11C13/0004 ,  G11C13/0007 ,  G11C14/00 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/2454

摘要： A non-volatile memory device having a three-dimensional (3D) structure includes a plurality of line-type horizontal electrode structures configured to include a plurality of interlayer dielectric layers and a plurality of horizontal electrodes that are alternately stacked over a substrate, a plurality of pillar-type vertical electrodes configured to protrude from the substrate while contacting sidewalls of the plurality of the horizontal electrode structures, and a memory layer interposed between the plurality of the horizontal electrode structures and the plurality of the vertical electrodes, and configured to have a resistance value that varies based on a bias applied to the plurality of the horizontal electrodes and the plurality of the vertical electrodes.

摘要翻译： 具有三维（3D）结构的非易失性存储器件包括多个线型水平电极结构，其被配置为包括交替层叠在衬底上的多个层间电介质层和多个水平电极，多个 构成为从所述基板突出而同时接触所述多个所述水平电极结构的侧壁的柱状垂直电极;以及插入在所述多个所述水平电极结构体与所述多个所述垂直电极之间的存储层， 电阻值基于施加到多个水平电极和多个垂直电极的偏压而变化。

公开(公告)号：US08637913B2

公开(公告)日：2014-01-28

申请号：US13304551

申请日：2011-11-25

申请人： Hyun-Seung Yoo ,  Eun-Seok Choi

发明人： Hyun-Seung Yoo ,  Eun-Seok Choi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.

摘要翻译： 非易失性存储器件包括从衬底垂直延伸并包括掺杂有第一杂质的第一区和设置在第一区下的第二区的通道，多个存储单元和选择晶体管沿着衬底 通道和插入在第一区域和第二区域之间的扩散阻挡层，其中第一杂质的密度高于第二区域的杂质密度。

公开(公告)号：US08730727B2

公开(公告)日：2014-05-20

申请号：US12907560

申请日：2010-10-19

申请人： Hyun-Seung Yoo ,  Eun-Seok Choi ,  Se-Jun Kim

发明人： Hyun-Seung Yoo ,  Eun-Seok Choi ,  Se-Jun Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.

摘要翻译： 3D非易失性存储器件包括在衬底上形成的板式下选择线，形成在下选择线中的下选择晶体管，堆叠在下选择晶体管上的多个存储单元，形成在上选晶体管上的上选晶体管 存储单元，以及形成在衬底上并与下部选择线间隔开的线型公共源极线。

公开(公告)号：US20120299076A1

公开(公告)日：2012-11-29

申请号：US13304551

申请日：2011-11-25

申请人： Hyun-Seung YOO ,  Eun-Seok Choi

发明人： Hyun-Seung YOO ,  Eun-Seok Choi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.

摘要翻译： 非易失性存储器件包括从衬底垂直延伸并包括掺杂有第一杂质的第一区和设置在第一区下的第二区的通道，多个存储单元和选择晶体管沿着衬底沿堆叠在衬底上 通道和插入在第一区域和第二区域之间的扩散阻挡层，其中第一杂质的密度高于第二区域的杂质密度。

公开(公告)号：US09053977B2

公开(公告)日：2015-06-09

申请号：US13610781

申请日：2012-09-11

申请人： Eun-Seok Choi ,  Hyun-Seung Yoo

发明人： Eun-Seok Choi ,  Hyun-Seung Yoo

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11573 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.

摘要翻译： 根据本发明的一个实施例的非易失性存储器件包括：包括P型杂质掺杂区的衬底，包括多个层间绝缘层的沟道结构，所述多个层间绝缘层交替层叠有多个沟道层 基板，与所述多个沟道层的侧壁接触的P型半导体图案，其中所述P型半导体图案的下端接触所述P型杂质掺杂区域，以及设置在所述P型掺杂区域的两侧的源极线 P型半导体图案并与多个沟道层的侧壁接触。

公开(公告)号：US20110090737A1

公开(公告)日：2011-04-21

申请号：US12907560

申请日：2010-10-19

申请人： Hyun-Seung Yoo ,  Eun-Seok Choi ,  Se-Jun Kim

发明人： Hyun-Seung Yoo ,  Eun-Seok Choi ,  Se-Jun Kim

IPC分类号： G11C16/04 ,  H01L29/772 ,  H01L21/336

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.

摘要翻译： 3D非易失性存储器件包括在衬底上形成的板式下选择线，形成在下选择线中的下选择晶体管，堆叠在下选择晶体管上的多个存储单元，形成在上选晶体管上的上选晶体管 存储单元，以及形成在衬底上并与下部选择线间隔开的线型公共源极线。

公开(公告)号：USD654478S1

公开(公告)日：2012-02-21

申请号：US29405087

申请日：2011-10-28

申请人： Chang-Soo Noh ,  You-Sun Ji ,  Se-Ra Park ,  Sang-On Choi ,  Eun-Seok Choi

设计人： Chang-Soo Noh ,  You-Sun Ji ,  Se-Ra Park ,  Sang-On Choi ,  Eun-Seok Choi

公开(公告)号：US06913967B2

公开(公告)日：2005-07-05

申请号：US10623098

申请日：2003-07-18

申请人： Eun-Seok Choi ,  Seung-Jin Yeom

发明人： Eun-Seok Choi ,  Seung-Jin Yeom

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75

摘要： The inventive ferroelectric memory device includes: a semiconductor substrate providing elements of a transistor; a first inter-layer insulating layer formed on the semiconductor substrate; a storage node contact connected to elements of the transistor by passing through the first inter-layer insulating layer; a barrier layer contacting simultaneously to the storage node contact and the first inter-layer insulating layer; a lower electrode having a space for isolating the first inter-layer insulating layer and being formed on the barrier layer; a glue layer being formed on the first inter-layer insulating layer and encompassing lateral sides of the lower electrode as filling the space; a second inter-layer insulating layer exposing a surface of the lower electrode and encompassing the glue layer; a ferroelectric layer formed on the glue layer including the second inter-layer insulating layer; and an upper electrode formed on the ferroelectric layer.

摘要翻译： 本发明的铁电存储器件包括：提供晶体管元件的半导体衬底; 形成在所述半导体基板上的第一层间绝缘层; 通过穿过所述第一层间绝缘层而连接到所述晶体管的元件的存储节点接触; 与所述存储节点接触部和所述第一层间绝缘层同时接触的阻挡层; 具有用于隔离所述第一层间绝缘层并形成在所述阻挡层上的空间的下电极; 胶层在第一层间绝缘层上形成，并且在下部电极的横向侧面填充空间; 第二层间绝缘层，暴露下电极的表面并包围胶层; 形成在包括第二层间绝缘层的胶层上的铁电层; 以及形成在强电介质层上的上电极。