公开(公告)号：US20120063251A1

公开(公告)日：2012-03-15

申请号：US13228102

申请日：2011-09-08

申请人： Jong Hyoung LIM ,  Sang Seok Kang ,  Hyung Shin Kwon

发明人： Jong Hyoung LIM ,  Sang Seok Kang ,  Hyung Shin Kwon

IPC分类号： G11C7/06

CPC分类号： G11C7/12

摘要： A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

摘要翻译： 半导体器件包括位线，互补位线，被配置为感测和放大位线和互补位线之间的电压差的读出放大器，以及电容调整电路，配置为调整互补位线的负载电容 响应于多个控制信号。

公开(公告)号：US20120052648A1

公开(公告)日：2012-03-01

申请号：US13221099

申请日：2011-08-30

申请人： Hyung-Shin Kwon ,  Hyung-Dong Kim

发明人： Hyung-Shin Kwon ,  Hyung-Dong Kim

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

摘要： A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

摘要翻译： 半导体器件可以包括取决于衬底上的位置的具有不同高度的下电极。 提供了与具有相对较大高度的下电极接触的支撑层图案。 支撑层图案设置在用于支撑下电极的下电极之间。 电介质层设置在下电极和支撑层图案上。 在电介质层上形成上电极，具有平坦的上表面。 在上电极上设置金属间介电层。 形成穿过金属间介电层并与上电极接触的金属接触。 金属接触件的底部部分形成在具有较小高度的下部电极下方的部分。 该设备具有较高的可靠性。

公开(公告)号：US07151031B2

公开(公告)日：2006-12-19

申请号：US10794445

申请日：2004-03-05

申请人： Hyung-Shin Kwon ,  Soon-Moon Jung

发明人： Hyung-Shin Kwon ,  Soon-Moon Jung

IPC分类号： H01L21/8234

CPC分类号： H01L21/823462 ,  H01L21/823456 ,  Y10S438/981

摘要： Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings. Second and third gate patterns are formed in the first and second gate openings respectively and the mask insulation layer is removed.

摘要翻译： 半导体器件包括在半导体衬底的第一有源区上的第一栅极图案。 第一栅极图案的顶部宽度基本上等于或小于第一栅极图案的底部宽度。 第二栅极图案设置在半导体衬底的第二有源区上。 第二栅极图案具有比第二栅极图案的底部宽度宽的顶部宽度。 通过在形成在半导体衬底的第一有源区上的第一栅极绝缘层上形成第一栅极图案来制造半导体器件。 在包括第一栅极图案的半导体基板上形成掩模绝缘层。 通过图案化掩模绝缘层来形成分别暴露半导体衬底的第二和第三有源区的第一和第二栅极开口。 第二和第三栅极绝缘层分别形成在暴露在第一和第二栅极开口中的第二和第三有源区上。 分别在第一和第二栅极开口中形成第二和第三栅极图案，并且去除掩模绝缘层。

公开(公告)号：US20060148153A1

公开(公告)日：2006-07-06

申请号：US11322440

申请日：2005-12-30

申请人： Hyung-Shin Kwon ,  Dong-Won Lee ,  Jun-Beom Park

发明人： Hyung-Shin Kwon ,  Dong-Won Lee ,  Jun-Beom Park

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807

摘要： Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.

摘要翻译： 提供制造半导体器件的方法。 NMOS晶体管和PMOS晶体管设置在基板上。 NMOS晶体管位于衬底的NMOS区域上，PMOS晶体管位于衬底的PMOS区域上。 第一绝缘层设置在NMOS晶体管上。 第一绝缘层具有第一压缩应力。 第二绝缘层设置在PMOS晶体管上。 第二绝缘层具有比第一绝缘层的应力消除比高的第二压缩应力和应力消除比。 在第一绝缘层和第二绝缘层上进行热处理工艺，使得第二绝缘层的第二压缩应力低于第一绝缘层的第一压缩应力。 还提供了相关设备。

公开(公告)号：US08619484B2

公开(公告)日：2013-12-31

申请号：US13228102

申请日：2011-09-08

申请人： Jong Hyoung Lim ,  Sang Seok Kang ,  Hyung Shin Kwon

发明人： Jong Hyoung Lim ,  Sang Seok Kang ,  Hyung Shin Kwon

IPC分类号： G11C7/02

CPC分类号： G11C7/12

摘要： A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

摘要翻译： 半导体器件包括位线，互补位线，被配置为感测和放大位线和互补位线之间的电压差的读出放大器，以及电容调整电路，配置为调整互补位线的负载电容 响应于多个控制信号。

公开(公告)号：US08558347B2

公开(公告)日：2013-10-15

申请号：US13780622

申请日：2013-02-28

申请人： Hyung-Shin Kwon ,  Hyung-Dong Kim

发明人： Hyung-Shin Kwon ,  Hyung-Dong Kim

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

摘要： A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

摘要翻译： 半导体器件可以包括取决于衬底上的位置的具有不同高度的下电极。 提供了与具有相对较大高度的下电极接触的支撑层图案。 支撑层图案设置在用于支撑下电极的下电极之间。 电介质层设置在下电极和支撑层图案上。 在电介质层上形成上电极，具有平坦的上表面。 在上电极上设置金属间介电层。 形成穿过金属间介电层并与上电极接触的金属接触。 金属接触件的底部部分形成在具有较小高度的下部电极下方的部分。 该设备具有较高的可靠性。

公开(公告)号：US20120026301A1

公开(公告)日：2012-02-02

申请号：US12861475

申请日：2010-08-23

申请人： Joo-won LEE ,  Tae-hwan CHA ,  Oh-yun KWON ,  Bong-geun LEE ,  Jun-hyung SHIN

发明人： Joo-won LEE ,  Tae-hwan CHA ,  Oh-yun KWON ,  Bong-geun LEE ,  Jun-hyung SHIN

IPC分类号： H04N13/04 ,  G06K9/00

CPC分类号： H04N13/122

摘要： Provided are a display device and method for altering images, the apparatus including: an input unit operable to receive a left image and a right image; and an image altering unit which is operable to alter the received left image and the received right image and to output an output image signal including the altered left image and the altered right image, wherein the left image is altered by changing a first portion, which is near a boundary area in the left image, and wherein the right image is altered by changing a second portion, which is near a boundary area in the right image.

摘要翻译： 提供了一种用于改变图像的显示装置和方法，该装置包括：可操作以接收左图像和右图像的输入单元; 以及图像改变单元，其可操作以改变所接收的左图像和所接收的右图像，并输出包括改变的左图像和改变的右图像的输出图像信号，其中通过改变第一部分来改变左图像， 靠近左图像中的边界区域，并且其中通过改变靠近右图像中的边界区域的第二部分来改变右图像。

公开(公告)号：USD611209S1

公开(公告)日：2010-03-02

申请号：US29314948

申请日：2009-05-12

申请人： Jae Hyung Shin

设计人： Jae Hyung Shin

公开(公告)号：US20070293030A1

公开(公告)日：2007-12-20

申请号：US11845707

申请日：2007-08-27

申请人： Hyung-Shin KWON ,  Joon-Yong JOO ,  Kwang-Ok KOH ,  Sung-Bong KIM

发明人： Hyung-Shin KWON ,  Joon-Yong JOO ,  Kwang-Ok KOH ,  Sung-Bong KIM

IPC分类号： H01L21/3205

CPC分类号： H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

摘要： The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

摘要翻译： 本发明提供一种具有硅化物薄膜的半导体器件及其形成方法。 半导体器件包括形成在半导体衬底的有源区上的栅极绝缘层。 在栅极绝缘层上形成栅电极。 在与栅电极相邻的有源区中形成杂质区。 诸如硅化钴薄膜的硅化物薄膜在杂质区域中形成为小于约200埃的厚度。

公开(公告)号：US07172944B2

公开(公告)日：2007-02-06

申请号：US11282156

申请日：2005-11-18

申请人： Hyung-Shin Kwon

发明人： Hyung-Shin Kwon

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/0266 ,  H01L29/41775 ,  H01L29/4933 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628

摘要： The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided. Further, the method includes defining an active region a semiconductor substrate, forming a gate electrode crossing over the active region, sequentially stacking first and second insulating layer patterns an active region adjacent to opposite sides of the gate electrode, forming a silicon epitaxial layer on the active region to be adjacent to edges of the first and second insulating layer patterns, and siliciding at least a part of the silicon epitaxial layer. The edge of the first insulating layer pattern contacting the active region is protruded from the edge of the second insulating layer pattern, and the silicon epitaxial layer covers the protruded edge of the first insulating layer pattern.

摘要翻译： 本发明提供一种具有升高的源极/漏极的半导体器件及其制造方法。 在半导体器件中，在半导体衬底的预定区域限定有源区，并且形成栅电极以跨越有源区。 第一绝缘层图案和第二绝缘层图案依次层叠在栅电极的侧壁上，并且在有源区上形成与第一绝缘层图案和第二绝缘层图案的边缘相邻的硅外延层。 第一绝缘层图案的边缘从第二绝缘层图案的边缘突出以被预定区域被硅化的硅外延层覆盖。 此外，该方法包括限定有源区域，形成跨越有源区域的栅电极的半导体衬底，顺序地将第一和第二绝缘层图案堆叠在与栅电极的相对侧相邻的有源区域上，在该栅极电极上形成硅外延层 有源区域与第一和第二绝缘层图案的边缘相邻，并且硅化硅外延层的至少一部分。 与有源区接触的第一绝缘层图案的边缘从第二绝缘层图案的边缘突出，并且硅外延层覆盖第一绝缘层图案的突出边缘。