公开(公告)号：US20060148153A1

公开(公告)日：2006-07-06

申请号：US11322440

申请日：2005-12-30

申请人： Hyung-Shin Kwon ,  Dong-Won Lee ,  Jun-Beom Park

发明人： Hyung-Shin Kwon ,  Dong-Won Lee ,  Jun-Beom Park

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807

摘要： Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.

摘要翻译： 提供制造半导体器件的方法。 NMOS晶体管和PMOS晶体管设置在基板上。 NMOS晶体管位于衬底的NMOS区域上，PMOS晶体管位于衬底的PMOS区域上。 第一绝缘层设置在NMOS晶体管上。 第一绝缘层具有第一压缩应力。 第二绝缘层设置在PMOS晶体管上。 第二绝缘层具有比第一绝缘层的应力消除比高的第二压缩应力和应力消除比。 在第一绝缘层和第二绝缘层上进行热处理工艺，使得第二绝缘层的第二压缩应力低于第一绝缘层的第一压缩应力。 还提供了相关设备。

公开(公告)号：US07348231B2

公开(公告)日：2008-03-25

申请号：US11322440

申请日：2005-12-30

申请人： Hyung-Shin Kwon ,  Dong-Won Lee ,  Jun-Beom Park

发明人： Hyung-Shin Kwon ,  Dong-Won Lee ,  Jun-Beom Park

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807

摘要： Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.

摘要翻译： 提供制造半导体器件的方法。 NMOS晶体管和PMOS晶体管设置在基板上。 NMOS晶体管位于衬底的NMOS区域上，PMOS晶体管位于衬底的PMOS区域上。 第一绝缘层设置在NMOS晶体管上。 第一绝缘层具有第一压缩应力。 第二绝缘层设置在PMOS晶体管上。 第二绝缘层具有比第一绝缘层的应力消除比高的第二压缩应力和应力消除比。 在第一绝缘层和第二绝缘层上进行热处理工艺，使得第二绝缘层的第二压缩应力低于第一绝缘层的第一压缩应力。 还提供了相关设备。

公开(公告)号：US08558347B2

公开(公告)日：2013-10-15

申请号：US13780622

申请日：2013-02-28

申请人： Hyung-Shin Kwon ,  Hyung-Dong Kim

发明人： Hyung-Shin Kwon ,  Hyung-Dong Kim

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

摘要： A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

摘要翻译： 半导体器件可以包括取决于衬底上的位置的具有不同高度的下电极。 提供了与具有相对较大高度的下电极接触的支撑层图案。 支撑层图案设置在用于支撑下电极的下电极之间。 电介质层设置在下电极和支撑层图案上。 在电介质层上形成上电极，具有平坦的上表面。 在上电极上设置金属间介电层。 形成穿过金属间介电层并与上电极接触的金属接触。 金属接触件的底部部分形成在具有较小高度的下部电极下方的部分。 该设备具有较高的可靠性。

公开(公告)号：US07172944B2

公开(公告)日：2007-02-06

申请号：US11282156

申请日：2005-11-18

申请人： Hyung-Shin Kwon

发明人： Hyung-Shin Kwon

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/0266 ,  H01L29/41775 ,  H01L29/4933 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628

摘要： The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided. Further, the method includes defining an active region a semiconductor substrate, forming a gate electrode crossing over the active region, sequentially stacking first and second insulating layer patterns an active region adjacent to opposite sides of the gate electrode, forming a silicon epitaxial layer on the active region to be adjacent to edges of the first and second insulating layer patterns, and siliciding at least a part of the silicon epitaxial layer. The edge of the first insulating layer pattern contacting the active region is protruded from the edge of the second insulating layer pattern, and the silicon epitaxial layer covers the protruded edge of the first insulating layer pattern.

摘要翻译： 本发明提供一种具有升高的源极/漏极的半导体器件及其制造方法。 在半导体器件中，在半导体衬底的预定区域限定有源区，并且形成栅电极以跨越有源区。 第一绝缘层图案和第二绝缘层图案依次层叠在栅电极的侧壁上，并且在有源区上形成与第一绝缘层图案和第二绝缘层图案的边缘相邻的硅外延层。 第一绝缘层图案的边缘从第二绝缘层图案的边缘突出以被预定区域被硅化的硅外延层覆盖。 此外，该方法包括限定有源区域，形成跨越有源区域的栅电极的半导体衬底，顺序地将第一和第二绝缘层图案堆叠在与栅电极的相对侧相邻的有源区域上，在该栅极电极上形成硅外延层 有源区域与第一和第二绝缘层图案的边缘相邻，并且硅化硅外延层的至少一部分。 与有源区接触的第一绝缘层图案的边缘从第二绝缘层图案的边缘突出，并且硅外延层覆盖第一绝缘层图案的突出边缘。

公开(公告)号：US20120052648A1

公开(公告)日：2012-03-01

申请号：US13221099

申请日：2011-08-30

申请人： Hyung-Shin Kwon ,  Hyung-Dong Kim

发明人： Hyung-Shin Kwon ,  Hyung-Dong Kim

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

摘要： A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

摘要翻译： 半导体器件可以包括取决于衬底上的位置的具有不同高度的下电极。 提供了与具有相对较大高度的下电极接触的支撑层图案。 支撑层图案设置在用于支撑下电极的下电极之间。 电介质层设置在下电极和支撑层图案上。 在电介质层上形成上电极，具有平坦的上表面。 在上电极上设置金属间介电层。 形成穿过金属间介电层并与上电极接触的金属接触。 金属接触件的底部部分形成在具有较小高度的下部电极下方的部分。 该设备具有较高的可靠性。

公开(公告)号：US07151031B2

公开(公告)日：2006-12-19

申请号：US10794445

申请日：2004-03-05

申请人： Hyung-Shin Kwon ,  Soon-Moon Jung

发明人： Hyung-Shin Kwon ,  Soon-Moon Jung

IPC分类号： H01L21/8234

CPC分类号： H01L21/823462 ,  H01L21/823456 ,  Y10S438/981

摘要： Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings. Second and third gate patterns are formed in the first and second gate openings respectively and the mask insulation layer is removed.

摘要翻译： 半导体器件包括在半导体衬底的第一有源区上的第一栅极图案。 第一栅极图案的顶部宽度基本上等于或小于第一栅极图案的底部宽度。 第二栅极图案设置在半导体衬底的第二有源区上。 第二栅极图案具有比第二栅极图案的底部宽度宽的顶部宽度。 通过在形成在半导体衬底的第一有源区上的第一栅极绝缘层上形成第一栅极图案来制造半导体器件。 在包括第一栅极图案的半导体基板上形成掩模绝缘层。 通过图案化掩模绝缘层来形成分别暴露半导体衬底的第二和第三有源区的第一和第二栅极开口。 第二和第三栅极绝缘层分别形成在暴露在第一和第二栅极开口中的第二和第三有源区上。 分别在第一和第二栅极开口中形成第二和第三栅极图案，并且去除掩模绝缘层。

公开(公告)号：US07312144B2

公开(公告)日：2007-12-25

申请号：US10932416

申请日：2004-09-02

申请人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

发明人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

IPC分类号： H01L21/4763

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/1104

摘要： An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

摘要翻译： 通过形成第一镶嵌互连结构来提供互连结构，所述第一镶嵌互连结构直接连接衬底中的第一有源区，衬底上的第一导电线和/或衬底上的第一电极，在衬底中具有第二有源区， 导电线和/或基板上的第二电极。 第二镶嵌互连结构可以将第一有源区，第一导线和/或第一电极直接连接到第二有源区，第二导线和/或第二电极。 第一有源区域，第一导电线路和/或连接到第二有源区域的第一电极，第一导电线路和/或第二电极通过第一镶嵌互连结构可以不同于第一有源区域，第一导电 线路和/或第一电极和第二有源区域，第二导电线路和/或第二电极通过第二镶嵌互连结构连接。

公开(公告)号：US06806180B2

公开(公告)日：2004-10-19

申请号：US10426266

申请日：2003-04-30

申请人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

发明人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

IPC分类号： H01L214763

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/1104

摘要： An interconnection structure is provided by foiling a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

摘要翻译： 通过形成第一镶嵌互连结构来提供互连结构，所述第一镶嵌互连结构直接连接衬底中的第一有源区，衬底上的第一导电线和/或衬底上的第一电极，在衬底中具有第二有源区，第二 导电线和/或基板上的第二电极。 第二镶嵌互连结构可以将第一有源区，第一导线和/或第一电极直接连接到第二有源区，第二导线和/或第二电极。 第一有源区域，第一导电线路和/或连接到第二有源区域的第一电极，第一导电线路和/或第二电极通过第一镶嵌互连结构可以不同于第一有源区域，第一导电 线路和/或第一电极和第二有源区域，第二导电线路和/或第二电极通过第二镶嵌互连结构连接。

公开(公告)号：US06551887B2

公开(公告)日：2003-04-22

申请号：US10198266

申请日：2002-07-16

申请人： Hyung-Shin Kwon ,  Joon-Yong Joo

发明人： Hyung-Shin Kwon ,  Joon-Yong Joo

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method of forming a semiconductor device spacer. In the method, a gate pattern is formed on a semiconductor substrate, and a first insulation layer, a second insulation layer, and a third insulation layer are sequentially formed over substantially the entire surface of the resultant structure. The second and third insulation layers are formed of the same material under a first pressure and a second pressure higher than the first pressure, respectively, and preferably of silicon nitride, using a low pressure chemical vapor deposition (LPCVD) technique. The third and second insulation layers are sequentially, anisotropically etched until the first insulation layer is exposed, thereby forming a spacer and a second insulation pattern. The spacer is selectively removed by an isotropic etching method, to minimize the recessed extent of the second insulation pattern. The exposed first insulation layer is etched to form a first insulation pattern.

摘要翻译： 本发明提供一种形成半导体器件间隔物的方法。 在该方法中，在半导体衬底上形成栅极图案，并且在所得结构的基本整个表面上依次形成第一绝缘层，第二绝缘层和第三绝缘层。 使用低压化学气相沉积（LPCVD）技术，第二和第三绝缘层分别由第一压力和高于第一压力的第二压力由相同的材料形成，并且优选由氮化硅形成。 对第三绝缘层和第二绝缘层进行各向异性蚀刻，直到第一绝缘层露出，从而形成间隔物和第二绝缘图案。 通过各向同性蚀刻方法选择性地去除间隔物，以使第二绝缘图案的凹陷范围最小化。 暴露的第一绝缘层被蚀刻以形成第一绝缘图案。

公开(公告)号：US07696048B2

公开(公告)日：2010-04-13

申请号：US11425065

申请日：2006-06-19

申请人： Hyung-Shin Kwon ,  Seug-Gyu Kim

发明人： Hyung-Shin Kwon ,  Seug-Gyu Kim

IPC分类号： H01L21/8232 ,  H01L21/8239

CPC分类号： H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116

摘要： A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch process. The increased height of the cell region spacers is adapted to further prevent over-etching during gate interconnect formation which would otherwise result in etching through the spacer to the substrate and subsequent short circuit. Therefore, it is also possible to prevent bridge defects due to over-etching, which occurs because the barrier metal layer for a subsequent interconnection contact is accidentally connected to the underlying substrate. Also, since the recessed spacer structure is provided in the peripheral region, it is possible to remarkably enhance a resistance distribution of a cobalt silicide layer occurring in a gate line width of 100 nm or less.

摘要翻译： 半导体器件在单元区域中具有正常的非凹入的间隔结构，并且在周边区域中形成有凹入的间隔结构。 凹陷的间隔结构通过蚀刻掩蔽细胞区域中的那些并且暴露在外围区域中的那些，然后进行蚀刻工艺而形成。 单元区域间隔物的增加的高度适于进一步防止在栅极互连形成期间的过度蚀刻，否则将导致通过间隔物蚀刻到衬底和随后的短路。 因此，也可以防止由于用于随后的互连接触的阻挡金属层意外地连接到下面的基板而发生的由于过蚀刻而引起的桥接缺陷。 此外，由于在周边区域设置凹陷的间隔结构，因此可以显着提高出现在100nm以下的栅极线宽度的硅化钴层的电阻分布。