Skateboard capable of providing self-propulsive force

    公开(公告)号:US09868048B2

    公开(公告)日:2018-01-16

    申请号:US15053104

    申请日:2016-02-25

    Applicant: In Tae Kang

    Inventor: In Tae Kang

    Abstract: The skateboard capable of providing the self-propulsive force includes: a board main body; a center rotation portion which allows a user of the skateboard to change a direction of the skateboard with one foot put thereon; a first footrest portion which is provided on one side of the board main body with respect to the center portion and moves the board main body through a left and right reciprocating movement of the footrest; a second footrest portion which is provided on the other side of the board main body with respect to the center portion and moves the board main body through a left/right reciprocating movement of the footrest; and an elastic guide portion which is provided between the board main body and the wheel assemblies and guides left/right reciprocating movements of the support members.

    Method and apparatus for reducing peak to average power ratio using peak windowing
    3.
    发明授权
    Method and apparatus for reducing peak to average power ratio using peak windowing 有权
    使用峰值窗口降低峰均功率比的方法和装置

    公开(公告)号:US08548092B2

    公开(公告)日:2013-10-01

    申请号:US13004271

    申请日:2011-01-11

    CPC classification number: H04L27/2624

    Abstract: A method and apparatus for reducing a Peak to Average Power Ratio (PAPR) using peak windowing is provided. In the apparatus, an absolute value calculator calculates an absolute value of an input signal, a subtractor subtracts a predetermined clipping threshold level from the absolute value, a smoothing unit performs smoothing on the subtracted signal according to a predetermined smoothing scheme and outputs a first smoothed signal, an adder adds the first smoothed signal to the clipping threshold level, an inverse calculator outputs a second smoothed signal by multiplying the clipping threshold level by an inverse of the added signal, and a multiplier outputs a final PAPR-reduced signal by multiplying the input signal by the second smoothed signal. The method and apparatus address an overcompensation problem while processing signals having a large bandwidth and a high data rate without delay, thereby minimizing the clipping influences on Bit Error Rate (BER) and Adjacent Channel Leakage Ratio (ACLR) performances.

    Abstract translation: 提供了一种使用峰值窗口降低峰均功率比(PAPR)的方法和装置。 在设备中,绝对值计算器计算输入信号的绝对值,减法器根据绝对值减去预定的限幅阈值电平,平滑单元根据预定的平滑方案对减法信号进行平滑处理,并输出第一个平滑 信号,加法器将第一平滑信号与削波阈值电平相加,逆计算器通过将削波阈值电平乘以相加信号的倒数来输出第二平滑信号,乘法器将最终的PAPR降低信号乘以 输入信号由第二平滑信号。 该方法和装置在不延迟地处理具有大带宽和高数据速率的信号的同时解决过度补偿问题,从而最小化对误码率(BER)和相邻信道泄漏比(ACLR)性能的削波影响。

    METHOD AND APPARATUS FOR REDUCING PEAK TO AVERAGE POWER RATIO USING PEAK WINDOWING
    4.
    发明申请
    METHOD AND APPARATUS FOR REDUCING PEAK TO AVERAGE POWER RATIO USING PEAK WINDOWING 有权
    使用峰值窗口降低平均功率比的峰值的方法和装置

    公开(公告)号:US20110182339A1

    公开(公告)日:2011-07-28

    申请号:US13004271

    申请日:2011-01-11

    CPC classification number: H04L27/2624

    Abstract: A method and apparatus for reducing a Peak to Average Power Ratio (PAPR) using peak windowing is provided. In the apparatus, an absolute value calculator calculates an absolute value of an input signal, a subtractor subtracts a predetermined clipping threshold level from the absolute value, a smoothing unit performs smoothing on the subtracted signal according to a predetermined smoothing scheme and outputs a first smoothed signal, an adder adds the first smoothed signal to the clipping threshold level, an inverse calculator outputs a second smoothed signal by multiplying the clipping threshold level by an inverse of the added signal, and a multiplier outputs a final PAPR-reduced signal by multiplying the input signal by the second smoothed signal. The method and apparatus address an overcompensation problem while processing signals having a large bandwidth and a high data rate without delay, thereby minimizing the clipping influences on Bit Error Rate (BER) and Adjacent Channel Leakage Ratio (ACLR) performances.

    Abstract translation: 提供了一种使用峰值窗口降低峰均功率比(PAPR)的方法和装置。 在设备中,绝对值计算器计算输入信号的绝对值,减法器根据绝对值减去预定的限幅阈值电平,平滑单元根据预定的平滑方案对减法信号进行平滑处理,并输出第一个平滑 信号,加法器将第一平滑信号与削波阈值电平相加,逆计算器通过将削波阈值电平乘以相加信号的倒数来输出第二平滑信号,乘法器将最终的PAPR降低信号乘以 输入信号由第二平滑信号。 该方法和装置在不延迟地处理具有大带宽和高数据速率的信号的同时解决过度补偿问题,从而最小化对误码率(BER)和相邻信道泄漏比(ACLR)性能的削波影响。

    APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING SIGNAL IN SINGLE CARRIER FREQUENCY DIVISION MULTIPLEXING ACCESS COMMUNICATION SYSTEM
    5.
    发明申请
    APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING SIGNAL IN SINGLE CARRIER FREQUENCY DIVISION MULTIPLEXING ACCESS COMMUNICATION SYSTEM 失效
    单载波频分多址接入通信系统发射/接收信号的装置及方法

    公开(公告)号:US20100322065A1

    公开(公告)日:2010-12-23

    申请号:US12795991

    申请日:2010-06-08

    CPC classification number: H04L5/003 H04L5/0007 H04L27/2618

    Abstract: A method and apparatus for transmitting a signal in a Single Carrier-Frequency Division Multiplexing Access (SC-FDMA) communication system are provided. The method includes determining if a Bandwidth Expansion Factor (BEF) Q is an integer, the BEF being determined as N/M according to a number N of subcarriers of a system band and a number M of subcarriers of an allocated band, expanding an input signal to be transmitted Q times in a time domain when the Q is an integer, generating an SC-FDMA signal, and transmitting the SC-FDMA signal.

    Abstract translation: 提供一种用于在单载波频分复用接入(SC-FDMA)通信系统中发送信号的方法和装置。 该方法包括:确定带宽扩展因子(BEF)Q是否为整数,根据系统频带的子载波的数目N和所分配频带的子载波数M来确定BEF为N / M,扩展输入 当Q为整数时,在时域中发送Q次的信号,产生SC-FDMA信号,并发送SC-FDMA信号。

    METHOD AND APPARATUS FOR REDUCING DIGITAL TO ANALOG CONVERSION (DAC) BITS IN FREQUENCY DIVISION MULTIPLE ACCESS (FDMA) SYSTEM
    6.
    发明申请
    METHOD AND APPARATUS FOR REDUCING DIGITAL TO ANALOG CONVERSION (DAC) BITS IN FREQUENCY DIVISION MULTIPLE ACCESS (FDMA) SYSTEM 失效
    用于减少频分多址(FDMA)系统中数字到模拟转换(DAC)位的方法和装置

    公开(公告)号:US20090154442A1

    公开(公告)日:2009-06-18

    申请号:US12337702

    申请日:2008-12-18

    Abstract: A method and an apparatus for reducing Digital-to-Analog Conversion (DAC) bits at a transmitter of a Frequency Division Multiple Access (FDMA) system reduces a number of the bits for conversion so as to save power and reduce the cost of operation. The method can include generating a digital signal gain control value and an analog signal gain control value using subcarrier allocation information, a required Signal to Noise Ratio (SNR), and a Peak to Average Power Ratio (PAPR); controlling a gain of a signal input to a digital-to-analog converter using the digital signal gain control value; converting a digital signal of the controlled gain to an analog signal using the digital-to-analog converter; and restoring an original signal by controlling a gain of a signal output from the digital-to-analog converter using the analog signal gain control value.

    Abstract translation: 用于减少频分多址(FDMA)系统的发射机处的数模转换(DAC)比特的方法和装置减少了用于转换的比特数,以节省功率并降低操作成本。 该方法可以包括使用子载波分配信息,所需的信噪比(SNR)和峰均功率比(PAPR)来产生数字信号增益控制值和模拟信号增益控制值; 使用数字信号增益控制值控制输入到数模转换器的信号的增益; 使用数模转换器将受控增益的数字信号转换为模拟信号; 以及通过使用模拟信号增益控制值控制从数模转换器输出的信号的增益来恢复原始信号。

    APPARATUS AND METHOD FOR BLOCK INTERLEAVING IN MOBILE COMMUNICATION SYSTEM
    7.
    发明申请
    APPARATUS AND METHOD FOR BLOCK INTERLEAVING IN MOBILE COMMUNICATION SYSTEM 审中-公开
    移动通信系统中的块交织的装置和方法

    公开(公告)号:US20090083514A1

    公开(公告)日:2009-03-26

    申请号:US12234788

    申请日:2008-09-22

    Abstract: A method and apparatus for block interleaving that eliminates the step of intermediary buffering. The method includes: (a) calculating a memory address at which first output data, of which number is equal to the number of rows of a first encoder is stored, (b) storing the first output data at the calculated memory address of a circular buffer, (c) storing second output data at an address which is incremented by a specific constant value from the calculated memory address of the circular buffer, and (d) storing (n+1)th output data at an address which is incremented by n from the calculated memory address of the circular buffer.

    Abstract translation: 一种用于块交织的方法和装置,其消除了中间缓冲的步骤。 该方法包括:(a)计算存储器地址,在该存储器地址处,存储第一个输出数据的数量等于第一个编码器的行数,(b)将第一个输出数据存储在计算的循环存储器地址 缓冲器,(c)将存储第二输出数据存储在从计算的循环缓冲器的存储器地址中增加特定常数值的地址处,以及(d)将第(n + 1)个输出数据存储在增加了 n从循环缓冲区的计算内存地址。

    Method and apparatus for reducing digital to analog conversion (DAC) bits in frequency division multiple access (FDMA) system
    9.
    发明授权
    Method and apparatus for reducing digital to analog conversion (DAC) bits in frequency division multiple access (FDMA) system 失效
    用于减少频分多址(FDMA)系统中的数模转换(DAC)位的方法和装置

    公开(公告)号:US08493954B2

    公开(公告)日:2013-07-23

    申请号:US12337702

    申请日:2008-12-18

    Abstract: A method and an apparatus for reducing Digital-to-Analog Conversion (DAC) bits at a transmitter of a Frequency Division Multiple Access (FDMA) system reduces a number of the bits for conversion so as to save power and reduce the cost of operation. The method can include generating a digital signal gain control value and an analog signal gain control value using subcarrier allocation information, a required Signal to Noise Ratio (SNR), and a Peak to Average Power Ratio (PAPR); controlling a gain of a signal input to a digital-to-analog converter using the digital signal gain control value; converting a digital signal of the controlled gain to an analog signal using the digital-to-analog converter; and restoring an original signal by controlling a gain of a signal output from the digital-to-analog converter using the analog signal gain control value.

    Abstract translation: 用于减少频分多址(FDMA)系统的发射机处的数模转换(DAC)比特的方法和装置减少了用于转换的比特数,以节省功率并降低操作成本。 该方法可以包括使用子载波分配信息,所需的信噪比(SNR)和峰均功率比(PAPR)来产生数字信号增益控制值和模拟信号增益控制值; 使用数字信号增益控制值控制输入到数模转换器的信号的增益; 使用数模转换器将受控增益的数字信号转换为模拟信号; 以及通过使用模拟信号增益控制值控制从数模转换器输出的信号的增益来恢复原始信号。

    Horse-riding bicycle
    10.
    发明授权

    公开(公告)号:US10328989B2

    公开(公告)日:2019-06-25

    申请号:US15982260

    申请日:2018-05-17

    Applicant: In Tae Kang

    Inventor: In Tae Kang

    Abstract: Provided is a horse-riding bicycle in which a horse-riding effect is obtained by performing both normal driving and horse-riding driving (swinging driving), a user is allowed to simply switch a driving mode between a normal driving mode and a horse-riding driving mode, and a horse-riding driving structure is improved to have a simple structure so that a reduction in costs is achieved and, further, a switching operation between the normal driving mode and the horse-riding driving mode is smoothly performed.

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