公开(公告)号：US08638585B2

公开(公告)日：2014-01-28

申请号：US13137409

申请日：2011-08-12

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C5/02

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US08565021B2

公开(公告)日：2013-10-22

申请号：US13137401

申请日：2011-08-11

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US20110299335A1

公开(公告)日：2011-12-08

申请号：US13137401

申请日：2011-08-11

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/10

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US20110302476A1

公开(公告)日：2011-12-08

申请号：US13137425

申请日：2011-08-15

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G06F12/00 ,  H03M13/05 ,  G06F11/10 ,  G06F13/28

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US20110302468A1

公开(公告)日：2011-12-08

申请号：US13137424

申请日：2011-08-15

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C29/52 ,  G06F11/22

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US20110302352A1

公开(公告)日：2011-12-08

申请号：US13137423

申请日：2011-08-15

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G06F12/02

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract translation: 存储器系统设置有处理器，主存储器和闪存。 通过实现加速和高数据可靠性，可以提高存储系统的性能。 存储器系统包括非易失性存储器件和被配置为驱动控制程序以控制非易失性存储器件的控制器。 即使在完成对非易失性存储器件的第一访问操作之前，控制程序也执行用于非易失性存储器件的第二访问操作。

公开(公告)号：US20110299338A1

公开(公告)日：2011-12-08

申请号：US13137422

申请日：2011-08-15

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US06982662B2

公开(公告)日：2006-01-03

申请号：US10795914

申请日：2004-03-08

Applicant: Jaehoon Heo

Inventor： Jaehoon Heo

IPC: H03M7/00

CPC classification number: G11B20/10527

Abstract: An apparatus and method for conversion of direct stream digital (DSD) signal samples to pulse code modulated (PCM) signal samples using a look-up table. The apparatus includes a first-in-first-out (FIFO) buffer that contains a plurality of bits from a DSD signal, the plurality of bits further divided into a plurality of words of the same size. The apparatus comprises a look-up table coupled to the FIFO buffer, the look-up table generating a result for each of the plurality of words. In one embodiment, the apparatus includes an accumulator coupled to the look-up table, the accumulator holding the results added together. After adding the result for the last word in the plurality of bits, the accumulator generates at an output a multiple bit PCM signal sample. The apparatus includes an address generator connected to the FIFO buffer and look-up table.

Abstract translation: 用于使用查找表将直接数字（DSD）信号样本转换成脉冲编码调制（PCM）信号样本的装置和方法。 该装置包括从DSD信号包含多个比特的先进先出（FIFO）缓冲器，该多个比特进一步被划分为相同大小的多个单词。 该装置包括耦合到FIFO缓冲器的查找表，查找表为多个单词中的每一个生成结果。 在一个实施例中，该装置包括耦合到查找表的累加器，该累加器将结果相加在一起。 在为多个位中的最后一个字添加结果之后，累加器在输出端产生多位PCM信号样本。 该装置包括连接到FIFO缓冲器和查找表的地址发生器。

公开(公告)号：US08760918B2

公开(公告)日：2014-06-24

申请号：US13137423

申请日：2011-08-15

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US08027194B2

公开(公告)日：2011-09-27

申请号：US12457485

申请日：2009-06-12

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: One embodiment of a nonvolatile memory device includes a memory cell array including a plurality of multi-level cells, and a control unit configured to determine a characteristic of data to be stored in the memory cell array. The control unit is configured to select one of plural multi-bit programming methods based on the determination. Data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit data when there is a program fail of most significant bit data.

Abstract translation: 非易失性存储器件的一个实施例包括包括多个多电平单元的存储单元阵列，以及配置为确定要存储在存储单元阵列中的数据的特性的控制单元。 控制单元被配置为基于该确定来选择多个多位编程方法之一。 数据根据所选择的多位编程方法存储在存储单元阵列中，并且当存在最高有效位数据的程序失败时，多个多位编程方法中的至少一个保持最低有效位数据。