公开(公告)号：US08705272B2

公开(公告)日：2014-04-22

申请号：US13137424

申请日：2011-08-15

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract translation: 存储器系统设置有处理器，主存储器和闪存。 通过实现加速和高数据可靠性，可以提高存储系统的性能。 存储器系统包括非易失性存储器件和被配置为驱动控制程序以控制非易失性存储器件的控制器。 即使在完成对非易失性存储器件的第一访问操作之前，控制程序也执行用于非易失性存储器件的第二访问操作。

公开(公告)号：US08625344B2

公开(公告)日：2014-01-07

申请号：US13137425

申请日：2011-08-15

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US20110307646A1

公开(公告)日：2011-12-15

申请号：US13137409

申请日：2011-08-12

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G06F12/00

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US08760918B2

公开(公告)日：2014-06-24

申请号：US13137423

申请日：2011-08-15

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US08027194B2

公开(公告)日：2011-09-27

申请号：US12457485

申请日：2009-06-12

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: One embodiment of a nonvolatile memory device includes a memory cell array including a plurality of multi-level cells, and a control unit configured to determine a characteristic of data to be stored in the memory cell array. The control unit is configured to select one of plural multi-bit programming methods based on the determination. Data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit data when there is a program fail of most significant bit data.

Abstract translation: 非易失性存储器件的一个实施例包括包括多个多电平单元的存储单元阵列，以及配置为确定要存储在存储单元阵列中的数据的特性的控制单元。 控制单元被配置为基于该确定来选择多个多位编程方法之一。 数据根据所选择的多位编程方法存储在存储单元阵列中，并且当存在最高有效位数据的程序失败时，多个多位编程方法中的至少一个保持最低有效位数据。

公开(公告)号：US20090310408A1

公开(公告)日：2009-12-17

申请号：US12457485

申请日：2009-06-12

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract translation: 存储器系统设置有处理器，主存储器和闪存。 通过实现加速和高数据可靠性，可以提高存储系统的性能。 存储器系统包括非易失性存储器件和被配置为驱动控制程序以控制非易失性存储器件的控制器。 即使在完成对非易失性存储器件的第一访问操作之前，控制程序也执行用于非易失性存储器件的第二访问操作。

公开(公告)号：US08638585B2

公开(公告)日：2014-01-28

申请号：US13137409

申请日：2011-08-12

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C5/02

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US08565021B2

公开(公告)日：2013-10-22

申请号：US13137401

申请日：2011-08-11

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US08412909B2

公开(公告)日：2013-04-02

申请号：US12755644

申请日：2010-04-07

Applicant: Wonmoon Cheon ,  Young-Goo Ko ,  Wonhee Cho ,  Yeon Ju Jeong ,  Donggi Lee ,  Hyuck-Sun Kwon

Inventor： Wonmoon Cheon ,  Young-Goo Ko ,  Wonhee Cho ,  Yeon Ju Jeong ,  Donggi Lee ,  Hyuck-Sun Kwon

IPC: G06F12/02

CPC classification number: G06F3/0644 ,  G06F3/0613 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7204 ,  G06F2212/7206

Abstract: A storage apparatus includes a memory unit and a controller to set up a memory space of the memory unit as a user data space and a spare space according to a signal representing at least one of the user data space and spare space. An electronic apparatus controls the storage apparatus, and a method controls at least one of the storage apparatus and the electronic apparatus to control a memory space of the storage apparatus.

Abstract translation: 存储装置包括存储器单元和控制器，用于根据表示用户数据空间和备用空间中的至少一个的信号，将存储器单元的存储器空间设置为用户数据空间和备用空间。 电子装置控制存储装置，并且控制存储装置和电子装置中的至少一个的方法来控制存储装置的存储空间。

公开(公告)号：US20110299335A1

公开(公告)日：2011-12-08

申请号：US13137401

申请日：2011-08-11

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/10

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.