Abstract:
A synchronous DC-DC regulator, adapted to receive a high side pulsed signal and a low side pulsed signal that is substantially the inverse of the high side pulsed signal. The regulator includes an inductor, and a capacitor having one port connected to ground, and having a second port providing an output voltage of the DC-DC regulator. A driver is provided for driving pulses of current to the inductor when the high side pulsed signal is asserted. An undercurrent sense circuit is adapted to sense a driving current flowing through the driver and to assert a disable signal when the driving current is less than a predetermined amount. An enable/disable circuit is adapted to allow the low side pulsed signal to turn the switch on when the disable signal is not asserted, and to not allow the low side pulsed signals from turning the switch on when the disable signal is asserted.
Abstract:
A DC/DC converter has a semiconductor switch coupled to an inductor, a capacitor and a rectifier. A comparator is coupled to across the rectifier to detect a polarity reversal during the second portion of converter operation to place the converter in a low power mode if the voltage across the rectifier is of an appropriate polarity for reverse current flow. The rectifier may be a synchronous rectifier transistor and the voltage converter placed in a low power mode when the polarity across the synchronous rectifier indicates that reverse current flow is possible. A timing circuit delays the generation of the control signal to place the converter in a low power mode until the steady state current is below a predetermined threshold for a predetermined amount of time. The synchronous rectifier may be turned OFF when the current through the converter falls below another predetermined threshold value and the voltage across the synchronous rectifier will become the voltage across the parasitic diode of the FET synchronous rectifier.
Abstract:
A multiple mode switching regulator with a bootstrap technique includes an inductor 20; a high side input switch 22 coupled to a first end of the inductor 20; a low side input switch 24 coupled to the first end of the inductor 20; a high side driver 34 coupled to a control node of the high side input switch 22; a low side driver 36 coupled to a control node of the low side input switch 24; a high side output switch 26 coupled to a second end of the inductor 20; a low side output switch 28 coupled to the second end of the inductor 20; a first bootstrap capacitor 30 coupled between the first end of the inductor 20 and a voltage supply node of the high side driver 34; a second bootstrap capacitor 32 coupled between the second end of the inductor 20 and a voltage supply node of the low side driver 36; and a first diode 40 coupled between the voltage supply node of the high side driver 34 and the voltage supply node of the low side driver 36. The two bootstrap capacitors 30 and 32 are employed on both sides of inductor 20 to provide gate voltage to high side input switch 22 through high side driver 34 in any mode of operation. This allows the regulator to work in three modes of operation without different external components or configurations depending on the mode.
Abstract:
A switched mode power supply has a high side switching transistor coupled between a voltage source and a load for generating the output voltage at the load. A driver circuit drives the high side switching transistor. A first resistor divider is coupled to the output voltage and has a first tap. An error amplifier has a first input coupled to the first tap and a compensated feedback loop. A second resistor divider is coupled to the output voltage and has a second tap, resistance of the second resistor divider being less than resistance of the first resistor divider. A switch is coupled to the second tap and to the first input of the error amplifier for connecting the second tap to the first input of the error amplifier when the output voltage of the switched mode power supply reaches a first predetermined voltage.
Abstract:
A switched mode power supply has a high side switching transistor coupled between a voltage source and a load for generating the output voltage at the load. A driver circuit drives the high side switching transistor. A first resistor divider is coupled to the output voltage and has a first tap. An error amplifier has a first input coupled to the first tap and a compensated feedback loop. A second resistor divider is coupled to the output voltage and has a second tap, resistance of the second resistor divider being less than resistance of the first resistor divider. A switch is coupled to the second tap and to the first input of the error amplifier for connecting the second tap to the first input of the error amplifier when the output voltage of the switched mode power supply reaches a first predetermined voltage.
Abstract:
A switching regulator having a control circuit that automatically senses when a low power mode should be initiated without the use of expensive external components nor an extensive amount of external components is disclosed herein. The switching regulator includes an input switching device, a driver, an inductor, a first output switching device, a second output switching device and an output node. The control circuit includes a low power switching device connected to the output node and the second end of the inductor. An amplifier connects the low power switching device and the first output switching device. A first current mirror couples to the amplifier to mirror the difference between the output current through the output load and the current supplied at the second end of the inductor. A second current mirror couples to the first current mirror to mirror the current difference through a current source and a capacitor connected in parallel across the current source. A comparator compares the voltage generated by the capacitor with a predetermined voltage source. A first and second AND gate couples to the comparator. The output of the first AND gate provides a entry signal that initiates the low power mode for the switching regulator. The second AND gate couples to receive this entry signal. The output of the first AND gate provides a exit signal that indicates when the switching regulator is not in low power mode. The first AND gate couples to receive this exit signal.