摘要:
A multiple mode switching regulator with a bootstrap technique includes an inductor 20; a high side input switch 22 coupled to a first end of the inductor 20; a low side input switch 24 coupled to the first end of the inductor 20; a high side driver 34 coupled to a control node of the high side input switch 22; a low side driver 36 coupled to a control node of the low side input switch 24; a high side output switch 26 coupled to a second end of the inductor 20; a low side output switch 28 coupled to the second end of the inductor 20; a first bootstrap capacitor 30 coupled between the first end of the inductor 20 and a voltage supply node of the high side driver 34; a second bootstrap capacitor 32 coupled between the second end of the inductor 20 and a voltage supply node of the low side driver 36; and a first diode 40 coupled between the voltage supply node of the high side driver 34 and the voltage supply node of the low side driver 36. The two bootstrap capacitors 30 and 32 are employed on both sides of inductor 20 to provide gate voltage to high side input switch 22 through high side driver 34 in any mode of operation. This allows the regulator to work in three modes of operation without different external components or configurations depending on the mode.
摘要:
An internal circuitry protection scheme which protects on-IC circuitry when an external regulator voltage pin is shorted to a higher voltage. The circuit prevents damage to the on-die circuitry that is on the internal voltage rail, by clamping the received voltage, thereby eliminating the chance of damaging the on die circuitry. The circuit offers protection even if the voltage difference is large, but the difference remains small between the internal rail and the external regulated voltage under normal operation.
摘要:
An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.
摘要:
A switch mode controller circuit includes: a hysteretic comparator HYST_COMP for monitoring an output of a switch mode circuit; a standard comparator PHASE_COMP for monitoring a phase of the switch mode circuit; a logic block having a first input coupled to a clock signal generator Oscillator, a second input coupled to an output of the hysteretic comparator HYST_COMP, and a third input coupled to an output of the standard comparator PHASE_COMP, wherein the logic block generates switching cycles based on a fixed ON/OFF time during a first part of a cycle and based on a hysteretic control during a second part of the cycle.
摘要:
A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.
摘要:
An integrated solution to power management and distribution on a power bus, such as needed for an IEEE 1394 compliant expansion board. The integrated circuit includes a uni-directional switch on the input and one or more bi-directional switches on one or more outputs. Current can flow from the system power supply to any connected peripherals via the uni-directional switch and bi-directional switches, or can flow from the peripheral having the highest voltage power supply to the other peripherals via the bi-directional switches, but current will not flow back to the main system because of the unidirectional switch connected to the system power supply. Over-current conditions are quickly detected and the bi-directional switch is opened to prevent damage or over-heating. The switches are preferably fabricated as power FETs using NMOS technology. Several integrated circuits can be cascaded together to accommodate multiple peripherals.
摘要:
One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.
摘要:
A circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a first terminal coupled to a power supply and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well 504 and a shunting bipolar transistor is formed between the n-well 504 and an n-doped guard ring 500 formed adjacent to the n-well in the p-doped substrate 508.
摘要:
A transistor including a source region 506 in a semiconductor body 502; a bulk region 508 in the semiconductor body adjacent the source region; a drain region in the semiconductor body adjacent the bulk region but opposite the source region, the drain region including doped regions 504,514 of n and p dopant types; and a field plate 516 formed over the semiconductor body adjacent the drain region between the drain region and the bulk region.
摘要:
A switching regulator having a control circuit that automatically senses when a low power mode should be initiated without the use of expensive external components nor an extensive amount of external components is disclosed herein. The switching regulator includes an input switching device, a driver, an inductor, a first output switching device, a second output switching device and an output node. The control circuit includes a low power switching device connected to the output node and the second end of the inductor. An amplifier connects the low power switching device and the first output switching device. A first current mirror couples to the amplifier to mirror the difference between the output current through the output load and the current supplied at the second end of the inductor. A second current mirror couples to the first current mirror to mirror the current difference through a current source and a capacitor connected in parallel across the current source. A comparator compares the voltage generated by the capacitor with a predetermined voltage source. A first and second AND gate couples to the comparator. The output of the first AND gate provides a entry signal that initiates the low power mode for the switching regulator. The second AND gate couples to receive this entry signal. The output of the first AND gate provides a exit signal that indicates when the switching regulator is not in low power mode. The first AND gate couples to receive this exit signal.