Abstract:
The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the high side transistor; pull down devices coupled to a control node of the high side transistor and to a control node of the low side transistor; and wherein the pull down devices are controlled by a pull down circuit including a Power On Reset circuit, monitoring the digital power supply such that the high side and low side transistors are OFF until the digital power supply has settled to a desired operating voltage.
Abstract:
A switching mode power supply utilizing an analog sampled data system in the feedback control loop in which the coefficients of the sampled data system are change by reprogramming a programmable nonvolatile memory when external LC values vary.
Abstract:
The voltage matching circuit includes: a first branch including a first transistor; a second branch including a second transistor; and a cascaded level shifter coupled between the first and second branches to match a voltage on the first transistor with a voltage on the second transistor.
Abstract:
A switched mode power supply has a high side switching transistor coupled between a voltage source and a load for generating the output voltage at the load. A driver circuit drives the high side switching transistor. A first resistor divider is coupled to the output voltage and has a first tap. An error amplifier has a first input coupled to the first tap and a compensated feedback loop. A second resistor divider is coupled to the output voltage and has a second tap, resistance of the second resistor divider being less than resistance of the first resistor divider. A switch is coupled to the second tap and to the first input of the error amplifier for connecting the second tap to the first input of the error amplifier when the output voltage of the switched mode power supply reaches a first predetermined voltage.
Abstract:
A switched mode power supply has a high side switching transistor coupled between a voltage source and a load for generating the output voltage at the load. A driver circuit drives the high side switching transistor. A first resistor divider is coupled to the output voltage and has a first tap. An error amplifier has a first input coupled to the first tap and a compensated feedback loop. A second resistor divider is coupled to the output voltage and has a second tap, resistance of the second resistor divider being less than resistance of the first resistor divider. A switch is coupled to the second tap and to the first input of the error amplifier for connecting the second tap to the first input of the error amplifier when the output voltage of the switched mode power supply reaches a first predetermined voltage.
Abstract:
The reference voltage generator for a switch mode regulator includes: a reference voltage source; a soft-start voltage generator; and a comparator having a directional offset for comparing an output of the reference voltage source with an output of the soft-start voltage generator. Because of the intentional directional offset, the pass switch does not turn ON during the transition from the ramp voltage to reference voltage, therefore reducing energy stored in the inductor. Thus the voltage overshoot is reduced during the end of the soft-start cycle.
Abstract:
The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the high side transistor; pull down devices coupled to a control node of the high side transistor and to a control node of the low side transistor; and wherein the pull down devices are controlled by a pull down circuit including a Power On Reset circuit, monitoring the digital power supply such that the high side and low side transistors are OFF until the digital power supply has settled to a desired operating voltage.
Abstract:
An operational amplifier having temperature-compensated offset correction. The amplifier includes an operational amplifier circuit, that has a first input field effect transistor (FET) having a gate connected to receive a first input signal, and a second input FET having a gate connected to receive a second input signal, the first and the second input FETs being connected together to receive a first bias current, and also being connected to respective sides of a first current mirror. A correction amplifier circuit is also provided, that has a first correction FET having a gate, and a second correction FET having a gate, the first and the second correction FETs being connected together to receive a second bias current, and also being connected to respective sides of a second current mirror. A resistor is arranged to have a fixed voltage provided across it, one terminal of the resistor being connected to the gate of the first correction FET and the other terminal of the resistor being connected to the gate of the second correction FET. A first bias FET is connected to conduct an “extra” current from the second correction FET that is blocked by the current mirror action from flowing through the second current mirror. A second bias FET is connected in current mirror configuration with the first bias FET to form a third current mirror, and is configured to mirror and scale the current through the first bias FET to a selected one of the first input FET and the second input FET.