Improved digital to analog converter providing self compensation to
offset errors
    5.
    发明授权
    Improved digital to analog converter providing self compensation to offset errors 失效
    改进的数模转换器提供自补偿来抵消错误

    公开(公告)号:US4107671A

    公开(公告)日:1978-08-15

    申请号:US719550

    申请日:1976-09-01

    CPC classification number: H03M1/60 H03M1/1023

    Abstract: An apparatus and method are disclosed for converting digital input signals of either polarity to representative analog output signals. An internal synchronous counter is clocked to generate internal digital signals of the same code as the input digital signal which are compared with the input digital signal which is stored in a bank of latches. Upon coincidence therebetween, an inhibiting pulse is produced from a coincidence circuit for disabling a buffer-integrator circuit. During the time interval between the enabling of the counter and the inhibiting pulse, the buffer-integrator integrates a single polarity reference voltage provided thereto to establish an analog voltage representative of the stored digital signal. Sample and hold circuits periodically sample the output of the integrator circuit to update and provide the analog output. Self compensation for operational amplifier offsets is provided during each conversion cycle. The converter is suitable to be fabricated using CMOS technology on a single chip and requires no ladder network.

    Abstract translation: 公开了一种将任一极性的数字输入信号转换成代表性的模拟输出信号的装置和方法。 内部同步计数器被计时以产生与输入数字信号相同的代码的内部数字信号,其与存储在一组锁存器中的输入数字信号进行比较。 在它们之间一致时,由禁止缓冲积分电路的符合电路产生禁止脉冲。 在计数器使能和禁止脉冲之间的时间间隔期间,缓冲积分器对提供的单极性参考电压进行积分,以建立表示存储的数字信号的模拟电压。 采样和保持电路周期性地对积分器电路的输出进行采样,以更新和提供模拟输出。 在每个转换周期内提供运算放大器偏置的自我补偿。 该转换器适用于使用CMOS技术在单个芯片上制造,不需要梯形网络。

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