公开(公告)号：US07469316B2

公开(公告)日：2008-12-23

申请号：US10364280

申请日：2003-02-10

Applicant: James M. Dodd

Inventor： James M. Dodd

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0215

Abstract: Machine-readable media, methods, and apparatus are described to issue transactions to a memory. In some embodiments, a memory controller may select pending transactions based upon selection criteria and may issue the selected transactions to memory. Further, the memory controller may close a page of the memory accessed by a write transaction in response to determining that the write transaction is the last write transaction of a series of one or more write transactions.

Abstract translation: 描述机器可读介质，方法和装置以向存储器发出事务。 在一些实施例中，存储器控制器可以基于选择标准来选择待处理的事务，并且可以将所选择的事务发布到存储器。 此外，响应于确定写入事务是一系列一个或多个写入事务的最后一个写入事务，存储器控制器可以关闭由写入事务访问的存储器的页面。

公开(公告)号：US06981089B2

公开(公告)日：2005-12-27

申请号：US10037436

申请日：2001-12-31

Applicant: James M. Dodd ,  Narendra S. Khandekar

Inventor： James M. Dodd ,  Narendra S. Khandekar

IPC: G06F13/40 ,  G06F13/36

CPC classification number: G06F13/4086

Abstract: Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.

Abstract translation: 公开了在每个存储器单元（例如，集成电路存储器件）中使用线路终端电路的存储器系统的方法和装置。 存储器单元包含终止控制逻辑，其设置可控终端电路的状态以控制数据总线上的反射。 终止控制逻辑从其存储单元的状态确定终端电路的适当状态，并且在某些情况下，从从命令/地址总线解码的命令中收集到的数据总线的近似状态。 单元上的终端配置寄存器可用于为每个单元状态和/或数据总线状态定义适当的终止状态。

公开(公告)号：US06925013B2

公开(公告)日：2005-08-02

申请号：US10786940

申请日：2004-02-24

Applicant: Robert J. Riesenman ,  James M. Dodd ,  Michael W. Williams

Inventor： Robert J. Riesenman ,  James M. Dodd ,  Michael W. Williams

IPC: G06F12/04 ,  G06F12/06 ,  G06F13/16 ,  G11C16/04

CPC classification number: G06F13/1626 ,  G06F12/04

Abstract: A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

公开(公告)号：US5640519A

公开(公告)日：1997-06-17

申请号：US528914

申请日：1995-09-15

Applicant: Brian K. Langendorf ,  James M. Dodd ,  George R. Hayek

Inventor： Brian K. Langendorf ,  James M. Dodd ,  George R. Hayek

IPC: G06F13/364 ,  G06F13/36 ,  G06F13/362

CPC classification number: G06F13/364

Abstract: An arbitration circuit which controls arbitration for a resource by a first plurality of agents including a latency sensitive agent. The arbitration circuit comprises a mapping circuit and an arbiter. The mapping circuit is coupled to the first plurality of agents in order to receive a resource request signal from the latency sensitive agent and thereafter produce a plurality of request signals identical to the resource request signal. These request signals are input into at least a first and second I/O ports of the arbiter. The arbiter, which is coupled to the mapping circuit, including a second plurality of I/O ports and a second plurality of control ports each corresponding to one of the I/O ports. The arbiter is configured to arbitrate request signals input into the second plurality of I/O ports including the plurality of request signals, to monitor which I/O port was last activated, and to deactivate a control port associated with the I/O port thereby producing a control signal. This control signal signals the mapping circuit to disable at least one of the plurality of request signals upon detecting that the control signal is associated with the first I/O port or the second I/O port.

Abstract translation: 仲裁电路，其由包括等待时间敏感代理的第一多个代理控制资源的仲裁。 仲裁电路包括映射电路和仲裁器。 映射电路耦合到第一多个代理，以便从等待时间敏感代理接收资源请求信号，然后产生与资源请求信号相同的多个请求信号。 这些请求信号被输入到仲裁器的至少第一和第二I / O端口中。 耦合到映射电路的仲裁器包括每个对应于一个I / O端口的第二多个I / O端口和第二多个控制端口。 仲裁器被配置为仲裁输入到包括多个请求信号的第二多个I / O端口的请求信号，以监视上一次激活的I / O端口，并且停用与I / O端口相关联的控制端口，从而 产生控制信号。 该控制信号在检测到控制信号与第一I / O端口或第二I / O端口相关联时，通知该映射电路来禁用多个请求信号中的至少一个。

公开(公告)号：US5603010A

公开(公告)日：1997-02-11

申请号：US580323

申请日：1995-12-28

Applicant: James M. Dodd ,  Richard Malinowski ,  Brian K. Langendorf ,  George R. Hayek

Inventor： James M. Dodd ,  Richard Malinowski ,  Brian K. Langendorf ,  George R. Hayek

IPC: G06F12/04 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F13/4239

Abstract: A method of improving computer system performance during memory reads. Prior art computer systems experience a considerable time penalty during microprocessor reads from system memory. This time penalty is mitigated by the method of the present invention, wherein data is speculatively retrieved from system memory upon receipt of a microprocessor read request. A microprocessor initiates a read request which is decoded by a memory controller. Before the decoding has completed, the memory controller speculatively begins to retrieve data from the system memory device. Thus if the decode step determines that the requested data is in system memory, the time required to retrieve the data is decreased.

Abstract translation: 一种在存储器读取期间提高计算机系统性能的方法。 现有技术的计算机系统在从系统存储器的微处理器读取期间经历相当多的时间损失。 通过本发明的方法减轻了该时间的损失，其中在接收到微处理器读取请求时，从系统存储器中推测性地检索数据。 微处理器启动由存储器控制器解码的读请求。 在解码完成之前，存储器控制器推测开始从系统存储器件中检索数据。 因此，如果解码步骤确定所请求的数据在系统存储器中，则检索数据所需的时间减少。

公开(公告)号：US07159066B2

公开(公告)日：2007-01-02

申请号：US10229655

申请日：2002-08-27

Applicant: James M. Dodd

Inventor： James M. Dodd

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0215

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor requests an external memory controller to close a storage location of a memory associated with a first memory transaction based upon a relationship between the first memory transaction and a second memory transaction.

Abstract translation: 描述了处理存储器事务的机器可读介质，方法和装置。 在一些实施例中，处理器基于第一存储器事务和第二存储器事务之间的关系，请求外部存储器控制器关闭与第一存储器事务相关联的存储器的存储位置。

公开(公告)号：US07120765B2

公开(公告)日：2006-10-10

申请号：US10284596

申请日：2002-10-30

Applicant: James M. Dodd ,  David Puffer

Inventor： James M. Dodd ,  David Puffer

IPC: G06F12/00

CPC classification number: G06F13/1626

Abstract: Machine-readable media, methods, and apparatus are described which order memory transactions to increase utilization of multiple memory channels. In some embodiments, a processor may determine an issue order for memory transactions based on the memory channels that are to service the memory transactions. In some embodiments, the processor attempts to obtain an issue order that minimizes or reduces the number of idle periods experienced by the memory channels. Further, the processor may issue the memory transactions to an external memory controller for servicing in the determined issue order.

Abstract translation: 描述了命令存储器事务以增加多个存储器通道的利用率的机器可读介质，方法和装置。 在一些实施例中，处理器可以基于要对存储器事务进行服务的存储器通道来确定存储器事务的发布顺序。 在一些实施例中，处理器尝试获得使存储器通道经历的空闲周期数量最小化或减少的问题顺序。 此外，处理器可以将存储器事务发布到外部存储器控制器，以按照确定的发布顺序进行维修。

公开(公告)号：US06742098B1

公开(公告)日：2004-05-25

申请号：US09678751

申请日：2000-10-03

Applicant: John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

Inventor： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

IPC: G06F1200

CPC classification number: G06F13/4256

Abstract: Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

Abstract translation: 公开了使用新的存储器模块结构的存储器系统的方法和装置。 在一个实施例中，存储器模块具有两个等级的存储器件，每个等级连接到两个64位宽数据寄存器中对应的一个。 数据寄存器连接到120：64多路复用器/解复用器的两个64位宽端口，64位宽数据缓冲器连接到多路复用器/解复用器的相对端口。 控制器同步数据寄存器，多路复用器/解复用器和数据缓冲器的操作。 在操作环境中，数据缓冲器连接到存储器总线。 当执行数据访问时，在单个数据访问期间，两者都与其对应的数据寄存器交换数据信令。 在缓冲器中，存储器总线数据传输发生在两个连续的时钟周期中，每个等级都有一个周期。 这允许存储器总线传输速率对于相同的存储器总线宽度和存储器件速度来说是双倍的。

公开(公告)号：US06530006B1

公开(公告)日：2003-03-04

申请号：US09664982

申请日：2000-09-18

Applicant: James M. Dodd ,  Michael W. Williams ,  John Halbert ,  Randy M. Bonella

Inventor： James M. Dodd ,  Michael W. Williams ,  John Halbert ,  Randy M. Bonella

IPC: G06F1200

CPC classification number: G06F13/4239

Abstract: The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.

Abstract translation: 本发明提供了一种用于在缓冲存储器系统中提供可靠传输的系统和方法。 该系统包括存储器件，存储器控制器，数据缓冲器，地址/命令缓冲器和时钟电路。 存储器控制器向存储器件发送数据，地址信息，状态信息和命令信息，并从存储器件接收数据。 缓冲器互连存储器件和存储器控制器。 时钟电路嵌入到addr / cmd缓冲区中。 时钟电路接收输入时钟，并将输出时钟输出到数据缓冲器和/或存储器件，以控制数据缓冲器和/或存储器件的时钟偏移。

公开(公告)号：US06507530B1

公开(公告)日：2003-01-14

申请号：US09967642

申请日：2001-09-28

Applicant: Michael W. Williams ,  James M. Dodd ,  Lloyd L Pollard, II ,  Nitin B Gupte

Inventor： Michael W. Williams ,  James M. Dodd ,  Lloyd L Pollard, II ,  Nitin B Gupte

IPC: G11C700

CPC classification number: G11C11/4078 ,  G11C7/04

Abstract: A memory system includes a plurality of memory device ranks. A memory controller having a connection with the plurality of memory device ranks is adapted to obtain command information being issued to one of the plurality of memory device ranks. The memory controller is also adapted to generate a power weight value based on a command type from the command information. The memory controller increments a power count of the one of the plurality of memory device ranks by the power weight value generated. The memory controller then compares the power count of the one of the plurality of memory device ranks to a threshold value set for the one of the plurality of memory device ranks. If it is determined that the power count exceeds the threshold value, the memory controller is adapted to throttle the one of the plurality of memory device ranks.

Abstract translation: 存储器系统包括多个存储器件等级。 具有与多个存储器装置等级的连接的存储器控​​制器适于获得被发布到多个存储器件等级之一的命令信息。 存储器控制器还适于基于来自命令信息的命令类型来生成功率权重值。 存储器控制器通过生成的功率权重值来增加多个存储器件等级中的一个的功率计数。 存储器控制器然后将多个存储器件等级中的一个的功率计数与为多个存储器件等级中的一个设置的阈值进行比较。 如果确定功率计数超过阈值，则存储器控制器适于调节多个存储器件等级中的一个。