公开(公告)号：US20060218467A1

公开(公告)日：2006-09-28

申请号：US11088562

申请日：2005-03-24

申请人： James Sibigtroth ,  Brian Cook ,  George Espinor ,  Clay Merritt ,  Bruce Morton

发明人： James Sibigtroth ,  Brian Cook ,  George Espinor ,  Clay Merritt ,  Bruce Morton

IPC分类号： G11C29/00

CPC分类号： G11C7/1045 ,  G11C7/1006 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/1804 ,  G11C2207/104

摘要： A memory has an ECC-enabled mode and an ECC-disabled mode in which the portion of the memory dedicated to use as storing ECC in the ECC-enabled mode is used for storing general purpose information (data) in the ECC-disabled mode. This is achieved in a non-volatile memory (NVM) by having the data and the portion of the memory with the corresponding ECC on the same word line. This is particularly important in an NVM because of complication relating to erase. In the ECC-enabled mode the ECC and corresponding data should be erased, programmed, and read together in order to avoid a significant layout and performance penalty. This is best achieved by having the ECC and the data on the same word line.

摘要翻译： 存储器具有ECC使能模式和ECC禁用模式，其中专用于在ECC启用模式中存储ECC的存储器的部分用于存储ECC禁用模式中的通用信息（数据）。 这通过在同一字线上具有相应的ECC的数据和存储器的一部分而在非易失性存储器（NVM）中实现。 这在NVM中特别重要，因为与擦除相关的并发症。 在启用ECC的模式下，ECC和相应的数据应该被擦除，编程和一起读取，以避免重大的布局和性能损失。 这最好通过将ECC和数据放在同一个字线上来实现。

公开(公告)号：US20060062070A1

公开(公告)日：2006-03-23

申请号：US10946951

申请日：2004-09-22

申请人： James Sibigtroth ,  George Espinor ,  Bruce Morton ,  Michael Wood

发明人： James Sibigtroth ,  George Espinor ,  Bruce Morton ,  Michael Wood

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/1006 ,  G11C5/145 ,  G11C7/24 ,  G11C16/12 ,  G11C2207/104

摘要： A data processing system (10) has an embedded non-volatile memory (22) that is programmed and erased by use of a high voltage provided by a charge pump (78). In order to prevent the non-volatile memory (22) from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump (78) is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit (110) in response to a program or erase operation being initiated. A control register (76) will provide a high voltage enable signal to the charge pump (78) only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit (110) may be enabled by another condition to protect the data processing system (10) from an authorized access.

摘要翻译： 数据处理系统（10）具有通过使用由电荷泵（78）提供的高电压来编程和擦除的嵌入式非易失性存储器（22）。 为了防止在低电源电压条件期间非易失性存储器（22）被无意地编程或擦除，当电源电压降低到预定值以下时，电荷泵（78）被禁用和放电。 这是通过响应于开始的编程或擦除操作启用低电压检测电路（110）来实现的。 仅当接收到电源有效信号时，控制寄存器（76）将向电荷泵（78）提供高电压使能信号。 在另一个实施例中，低电压检测电路（110）可以被另一条件启用，以保护数据处理系统（10）免受授权访问。

公开(公告)号：US20060028898A1

公开(公告)日：2006-02-09

申请号：US10912824

申请日：2004-08-06

申请人： James Sibigtroth ,  George Espinor ,  Bruce Morton

发明人： James Sibigtroth ,  George Espinor ,  Bruce Morton

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C16/06 ,  G11C16/24 ,  G11C2207/005 ,  G11C2216/22

摘要： A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being erased. In one example, the isolation circuit (16) electrically couples the segments during a read or program of memory cells located on the second segment (Seg2 BL0). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.