公开(公告)号：US06915480B2

公开(公告)日：2005-07-05

申请号：US10029704

申请日：2001-12-21

Applicant: Mauricio Calle ,  Joel R. Davidson ,  James T. Kirk ,  Betty A. McDaniel ,  Maurice A. Uebelhor

Inventor： Mauricio Calle ,  Joel R. Davidson ,  James T. Kirk ,  Betty A. McDaniel ,  Maurice A. Uebelhor

IPC: G06F11/00 ,  H03M13/00 ,  H04L1/00

CPC classification number: H04L1/201 ,  H04L1/0061 ,  H04L1/0082 ,  H04L2001/0092

Abstract: A network processor or other type of processor includes first classification circuitry, scheduling circuitry and second classification circuitry. The first classification circuitry is configured to determine for a given packet received by the processor whether the packet has one or more errors. The scheduling circuitry in an illustrative embodiment receives an indication of the error determination made by the first classification circuitry, and based on the indication controls the dropping of the given packet from the processor memories if the packet has one or more errors, e.g., via a flush transmit command. The second classification circuitry, which may be implemented as a single classification engine or a set of such engines, may be configured to perform at least one classification operation for the given packet, e.g., if the packet is supplied thereto by the scheduling circuitry.

Abstract translation: 网络处理器或其他类型的处理器包括第一分类电路，调度电路和第二分类电路。 第一分类电路被配置为确定由处理器接收到的给定分组数据包是否具有一个或多个错误。 说明性实施例中的调度电路接收由第一分类电路作出的错误确定的指示，并且如果分组具有一个或多个错误，则基于该指示控制来自处理器存储器的给定分组的丢弃，例如，经由 flush发送命令。 可以被实现为单个分类引擎或一组这样的引擎的第二分类电路可以被配置为对给定分组执行至少一个分类操作，例如，如果分组被调度电路提供给它。

公开(公告)号：US06804692B2

公开(公告)日：2004-10-12

申请号：US10037082

申请日：2001-12-21

Applicant: Joel R. Davidson ,  James T. Kirk ,  Mauricio Calle

Inventor： Joel R. Davidson ,  James T. Kirk ,  Mauricio Calle

IPC: G06F700

CPC classification number: H04L69/12

Abstract: A method and apparatus for reassembling data blocks back into their constituent data packets in a network processor. Each data block associated with a packet is assigned a unique queue identifier for use in assembling all blocks from the same packet. The packet is also assigned a packet identifier, a start of packet identifier and an end of packet identifier for use by downstream network processors to process the packet. The blocks are assembled according to the assigned queue identifier until the last block of a packet is received, at which time the packet reassembly is complete.

Abstract translation: 一种在网络处理器中将数据块重组成其组成数据分组的方法和装置。 与分组相关联的每个数据块被分配唯一的队列标识符，用于组合来自相同分组的所有块。 分组还被分配了分组标识符，分组标识符的开始和分组标识符的结尾，以供下游网络处理器使用以处理分组。 这些块根据分配的队列标识符进行组装，直到接收到分组的最后一个块，此时分组重组完成。

公开(公告)号：US07246102B2

公开(公告)日：2007-07-17

申请号：US10037040

申请日：2001-12-21

Applicant: Betty A. McDaniel ,  William Edward Baker ,  Narender R. Vangati ,  Mauricio Calle ,  James T. Kirk

Inventor： Betty A. McDaniel ,  William Edward Baker ,  Narender R. Vangati ,  Mauricio Calle ,  James T. Kirk

IPC: G06F17/00 ,  G06F7/00 ,  G06N5/02 ,  H04L12/28

CPC classification number: G06N5/02 ,  Y10S706/934 ,  Y10S707/99942

Abstract: A decision tree, representing a knowledge base, is segmented into at least two decision tree portions. The lower portion includes the tree entry point and is stored in a memory element with a faster access time than the upper portion, which includes the terminating element of the decision tree. Thus during the process of reading the tree entries for comparing them with the search object, the search entries in the lower portion of the tree can be read faster than the search entries in the upper portion, resulting in a faster traversal through the entire decision tree.

Abstract translation: 代表知识库的决策树被分割成至少两个决策树部分。 下部包括树入口点，并且被存储在具有比包括决策树的终止元素的上部更快的访问时间的存储元件中。 因此，在读取用于将它们与搜索对象进行比较的树条目的过程中，树的下部的搜索条目可以比上部的搜索条目更快地读取，导致通过整个决策树的更快的遍历 。

公开(公告)号：US20140315760A1

公开(公告)日：2014-10-23

申请号：US14234134

申请日：2012-07-20

Applicant: Daniel M. Ratner ,  Jill M. Johnsen ,  James T. Kirk ,  José A. López ,  Norman D. Brault ,  Shaoyi Jiang

Inventor： Daniel M. Ratner ,  Jill M. Johnsen ,  James T. Kirk ,  José A. López ,  Norman D. Brault ,  Shaoyi Jiang

IPC: G01N33/543 ,  G01N33/80

CPC classification number: G01N33/54373 ,  G01N21/75 ,  G01N33/80

Abstract: Photonic devices, systems, and methods for detecting an analyte in a biological solution (e.g., whole blood) are provided. Representative photonic devices are optical ring resonators having nanoscale features and micron-sized diameters. Due to the compact size of these devices, many resonators can be disposed on a single substrate and tested simultaneously as a sample is passed over the devices. Typical analytes include blood cells, antibodies, and pathogens, as well as compounds indicative of the presence of blood cells or pathogens (e.g., serology). In certain embodiments, blood type can be determined through photonic sensing using a combination of direct detection of blood cells and serology. By combining the detection signals of multiple devices, the type of blood can be determined.

Abstract translation: 提供了用于检测生物溶液（例如全血）中的分析物的光子器件，系统和方法。 代表性的光子器件是具有纳米尺度特征和微米尺寸直径的光学环形谐振器。 由于这些器件的紧凑尺寸，许多谐振器可以被布置在单个衬底上并且当样品通过器件时同时测试。 典型的分析物包括血细胞，抗体和病原体，以及指示存在血细胞或病原体的化合物（例如血清学）。 在某些实施方案中，血液类型可以通过使用血细胞直接检测和血清学的组合的光子感测来确定。 通过组合多个装置的检测信号，可以确定血液的类型。

公开(公告)号：US08782287B2

公开(公告)日：2014-07-15

申请号：US10029679

申请日：2001-12-21

Applicant: Gregg A. Bouchard ,  Mauricio Calle ,  Joel R. Davidson ,  Michael W. Hathaway ,  James T. Kirk ,  Christopher Brian Walton

Inventor： Gregg A. Bouchard ,  Mauricio Calle ,  Joel R. Davidson ,  Michael W. Hathaway ,  James T. Kirk ,  Christopher Brian Walton

IPC: G06F15/16 ,  H04L12/56 ,  H04L12/54

CPC classification number: H04L49/9094 ,  H04L45/00 ,  H04L45/60 ,  H04L47/50 ,  H04L49/90 ,  H04L49/9042

Abstract: A packet processing system comprises first processing circuitry for performing a first function, and first memory circuitry coupled to the first processing circuitry for storing received packets, wherein at least a portion of the packets stored by the first memory circuitry are usable by the first processing circuitry in accordance with the first function. The packet processing system further comprises at least second processing circuitry for performing a second function, and at least second memory circuitry coupled to the second processing circuitry for storing at least a portion of the same packets stored in the first memory circuitry, wherein at least a portion of the packets stored in the second memory circuitry are usable by the second processing circuitry in accordance with the second function. In an illustrative embodiment, the first processing circuitry and the second processing circuitry operate in a packet switching device such as a router. In such case, the first processing circuitry and the second processing circuitry operate between a packet network interface and a switch fabric of the packet switching device.

Abstract translation: 分组处理系统包括用于执行第一功能的第一处理电路和耦合到第一处理电路的第一存储器电路，用于存储所接收的分组，其中由第一存储器电路存储的分组的至少一部分可由第一处理电路 按照第一个功能。 分组处理系统还包括用于执行第二功能的至少第二处理电路，以及耦合到第二处理电路的至少第二存储器电路，用于存储存储在第一存储器电路中的相同分组的至少一部分，其中至少一个 存储在第二存储器电路中的分组的部分可以由第二处理电路根据第二功能使用。 在说明性实施例中，第一处理电路和第二处理电路在诸如路由器的分组交换设备中操作。 在这种情况下，第一处理电路和第二处理电路在分组网络接口和分组交换设备的交换结构之间操作。

公开(公告)号：US09599613B2

公开(公告)日：2017-03-21

申请号：US14234134

申请日：2012-07-20

Applicant: Daniel M. Ratner ,  Jill M. Johnsen ,  James T. Kirk ,  José A. López ,  Norman D. Brault ,  Shaoyi Jiang

Inventor： Daniel M. Ratner ,  Jill M. Johnsen ,  James T. Kirk ,  José A. López ,  Norman D. Brault ,  Shaoyi Jiang

IPC: G01N33/80 ,  G01N33/543 ,  G01N21/75

CPC classification number: G01N33/54373 ,  G01N21/75 ,  G01N33/80

Abstract: Photonic devices, systems, and methods for detecting an analyte in a biological solution (e.g., whole blood) are provided. Representative photonic devices are optical ring resonators having nanoscale features and micron-sized diameters. Due to the compact size of these devices, many resonators can be disposed on a single substrate and tested simultaneously as a sample is passed over the devices. Typical analytes include blood cells, antibodies, and pathogens, as well as compounds indicative of the presence of blood cells or pathogens (e.g., serology). In certain embodiments, blood type can be determined through photonic sensing using a combination of direct detection of blood cells and serology. By combining the detection signals of multiple devices, the type of blood can be determined.

公开(公告)号：US07113518B2

公开(公告)日：2006-09-26

申请号：US10025352

申请日：2001-12-19

Applicant: Mauricio Calle ,  Joel R. Davidson ,  Michael W. Hathaway ,  James T. Kirk

Inventor： Mauricio Calle ,  Joel R. Davidson ,  Michael W. Hathaway ,  James T. Kirk

IPC: H04L12/56 ,  G06F13/00 ,  G06F15/173

CPC classification number: H04L43/18 ,  H04L49/103 ,  H04L49/25

Abstract: A network processor or other type of processor includes a packet analyzer and first memory circuitry operatively coupled to the packet analyzer. The packet analyzer is operative to at least partially analyze one or more packets received by the processor in order to determine for a given one of the packets a portion of the packet to be stored in the first memory circuitry. The portion of the given packet when stored in the first memory circuitry is thereby made accessible for subsequent processing within the processor, without requiring access to second memory circuitry associated with the processor and configured to store substantially the entire given packet. The packet analyzer may be configured to utilize a value stored in a register of the processor to determine the portion of the given packet to be stored in the first memory circuitry. The register may be one of a number of registers which implement a look-up table accessible to the packet analyzer. The look-up table includes multiple entries, each having packet categorizing information, such as port number or packet flow identifier, and an associated number of blocks of the packet to be stored in the first memory circuitry. The value stored in a given one of the registers may be dynamically updatable under control of a host device operatively coupled to the processor.

公开(公告)号：US07043544B2

公开(公告)日：2006-05-09

申请号：US10029703

申请日：2001-12-21

Applicant: William E. Baker ,  Mauricio Calle ,  James T. Kirk ,  Betty A. McDaniel

Inventor： William E. Baker ,  Mauricio Calle ,  James T. Kirk ,  Betty A. McDaniel

IPC: G06F15/16

CPC classification number: H04L29/06 ,  H04L49/103 ,  H04L49/30 ,  H04L69/22

Abstract: A network processor or other type of processor includes classification circuitry and memory circuitry coupled to the classification circuitry. The memory circuitry is configured to store at least a portion of at least a given one of a number of packets to be processed by the classification circuitry. The classification circuitry implements a non-sequential packet classification process for at least a subset of the packets including the given packet. For example, in an embodiment in which the given packet is generated in accordance with multiple embedded protocols, the non-sequential packet classification process allows the processor to return from a given point within the packet, at which a final one of the protocols is identified, to a beginning of the packet, through the use of a “skip to beginning” instruction. The skip to beginning instruction may be configured to allow the processor to skip back to a particular bit, e.g., a first bit, of the given packet at a time during the classification process after which the particular bit has been processed, such that multiple passes of the classification process can be performed on the given packet. The processor may be configured as a network processor integrated circuit to provide an interface between a network from which the packet is received and a switch fabric in a router or switch.