公开(公告)号：US08246184B2

公开(公告)日：2012-08-21

申请号：US12162841

申请日：2007-02-06

申请人： Jean-Charles Souriau ,  Nicolas Sillon ,  Jean-Pierre Joly

发明人： Jean-Charles Souriau ,  Nicolas Sillon ,  Jean-Pierre Joly

IPC分类号： G02B27/00

CPC分类号： G02B5/23 ,  G02B5/201 ,  G02C7/101 ,  G02C2202/18

摘要： A novel method makes it possible to form cavities intended to contain a liquid with determined optical properties within a film for optical use. The walls (38) of the cavities (40) are formed by plasma etching of a layer of transparent or light absorbent material (30, 34) transferred onto a microtechnological substrate, the walls (38) having a structured profile in order to limit the parasitic phenomena of light diffusion and diffraction.

摘要翻译： 一种新颖的方法使得可以形成旨在含有在用于光学用途的膜内具有确定的光学性质的液体的空腔。 空腔（40）的壁（38）通过等离子体蚀刻形成，其中转移到微技术基板上的透明或光吸收材料层（30,34），壁（38）具有结构化轮廓以限制 光扩散和衍射的寄生现象。

公开(公告)号：US08048766B2

公开(公告)日：2011-11-01

申请号：US10561299

申请日：2004-06-23

申请人： Jean-Pierre Joly ,  Laurent Ulmer ,  Guy Parat

发明人： Jean-Pierre Joly ,  Laurent Ulmer ,  Guy Parat

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L29/06 ,  H01L27/08 ,  H01L21/02

CPC分类号： B81C1/00253 ,  H01L21/2007 ,  H01L21/8221 ,  H01L25/16 ,  H01L25/50 ,  H01L27/0688 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.

摘要翻译： 制造包含有源元件和无源元件的集成电路的管芯的方法包括制备含有至少一种活性组分的活性组分的第一衬底和含有诸如钙钛矿或MEMS的无源组分的关键组分的第二衬底， 并通过层转移结合两个衬底。 该方法提供了诸如MEMS与晶体管的器件的改进的单片集成。

公开(公告)号：US07763915B2

公开(公告)日：2010-07-27

申请号：US11654660

申请日：2007-01-18

申请人： Jean-Pierre Joly ,  Olivier Faynot ,  Laurent Clavelier

发明人： Jean-Pierre Joly ,  Olivier Faynot ,  Laurent Clavelier

IPC分类号： H01L29/80

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

摘要翻译： 三维集成CMOS电路形成在混合基板中。 在具有（100）取向的第一半导体硅层中，在底层形成n-MOS型晶体管，该层可以是张力应变的。 在顶级，在具有（110）取向的锗的优选单晶和压缩应变的第二半导电层中形成p-MOS晶体管。 第二半导电层被转移到其中预先形成n-MOS晶体管的第一块，然后形成p-MOS晶体管。

公开(公告)号：US07153747B2

公开(公告)日：2006-12-26

申请号：US10484056

申请日：2002-07-16

申请人： Jean-Pierre Joly

发明人： Jean-Pierre Joly

IPC分类号： H01L21/336

CPC分类号： H01L29/78684 ,  H01L21/28255 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66621 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78636

摘要： A process for producing a MOS-type transistor includes providing a substrate comprising a thin layer of silicon (26), integral with an insulating support (14), and covered with a superficial layer (28) of a semi-conductor material, local etching of the superficial layer to expose the silicon layer in at least one channel region, formation of an insulated gate (50) above the silicon layer in the channel region, and formation of a source and a drain on either side of the channel region, the source and drain extending in the layer of silicon and in the superficial layer.

摘要翻译： 一种制造MOS型晶体管的方法，包括提供包括与绝缘支撑件（14）成一体并且被半导体材料的表面层（28）覆盖的薄的薄层（26）的基板，局部蚀刻 的表面层以在至少一个沟道区域中露出硅层，在沟道区域中的硅层之上形成绝缘栅极（50），以及在沟道区域的任一侧上形成源极和漏极， 源极和漏极在硅层和表面层中延伸。

公开(公告)号：US20060252229A1

公开(公告)日：2006-11-09

申请号：US10561299

申请日：2004-06-23

申请人： Jean-Pierre Joly ,  Laurent Ulmer ,  Guy Parat

发明人： Jean-Pierre Joly ,  Laurent Ulmer ,  Guy Parat

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/46

CPC分类号： B81C1/00253 ,  H01L21/2007 ,  H01L21/8221 ,  H01L25/16 ,  H01L25/50 ,  H01L27/0688 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.

摘要翻译： 制造包含有源元件和无源元件的集成电路的管芯的方法包括制备含有至少一种活性组分的活性组分的第一衬底和含有诸如钙钛矿或MEMS的无源组分的关键组分的第二衬底， 并通过层转移结合两个衬底。 该方法提供了诸如MEMS与晶体管的器件的改进的单片集成。

公开(公告)号：US06383972B1

公开(公告)日：2002-05-07

申请号：US09555037

申请日：2000-05-23

申请人： Philippe Parmentier ,  Jean-Pierre Joly ,  Alain Perrard

发明人： Philippe Parmentier ,  Jean-Pierre Joly ,  Alain Perrard

IPC分类号： B01J2118

CPC分类号： B01J35/06 ,  B01J21/18 ,  B01J23/462 ,  C07C29/141 ,  D01F9/16 ,  C07C31/26

摘要： A carbon fiber fabric having large specific surface area is made using a rayon precursor, and a catalyst is fixed on the fabric by impregnation or by cationic exchange. The carbon fiber fabric has pores with a mean size lying in the range 0.3 nm to 3 nm, a carbon content greater than 99%, and a high density of functional groups per unit area which favors the dispersion of metal catalyst in the form of fine particles and which is good for highly selective catalytic reactions in fine chemistry.

摘要翻译： 使用人造丝前体制造具有大比表面积的碳纤维织物，并通过浸渍或阳离子交换将催化剂固定在织物上。 碳纤维织物具有平均尺寸在0.3nm至3nm的范围内，碳含量大于99％的孔，并且每单位面积的高官能团密度有利于金属催化剂以精细形式的分散 颗粒，对精细化学中的高选择性催化反应有好处。

公开(公告)号：US20070170471A1

公开(公告)日：2007-07-26

申请号：US11654660

申请日：2007-01-18

申请人： Jean-Pierre Joly ,  Olivier Faynot ,  Laurent Clavelier

发明人： Jean-Pierre Joly ,  Olivier Faynot ,  Laurent Clavelier

IPC分类号： H01L29/80

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

摘要翻译： 三维集成CMOS电路形成在混合基板中。 在具有（100）取向的第一半导体硅层中，在底层形成n-MOS型晶体管，该层可以是张力应变的。 在顶级，在具有（110）取向的锗的优选单晶和压缩应变的第二半导电层中形成p-MOS晶体管。 第二半导电层被转移到其中预先形成n-MOS晶体管的第一块，然后形成p-MOS晶体管。

公开(公告)号：US06197695B1

公开(公告)日：2001-03-06

申请号：US09419303

申请日：1999-10-15

申请人： Jean-Pierre Joly ,  Bernard Aspar ,  Béatrice Biasse ,  Marc Zussy

发明人： Jean-Pierre Joly ,  Bernard Aspar ,  Béatrice Biasse ,  Marc Zussy

IPC分类号： H01L21311

CPC分类号： H01L21/84 ,  H01L21/7624 ,  H01L21/8221 ,  H01L2924/00011 ,  Y10S438/906 ,  Y10S438/974 ,  H01L2224/80001

摘要： This invention relates to a process for the manufacture of one electronic structure comprising at least one active component and at least one passive component or element on a support substrate made of an insulating material. A characteristic process comprises the following steps: make the active component in a surface layer made of semiconducting material from an initial substrate comprising a wafer of semiconducting material supporting the said surface layer, make electrical insulation areas capable of insulating the passive component or element from the active component, make the passive component or element on and/or in the electrical insulation areas, prepare the surface of the initial substrate face with the said electronic structure to make this face compatible for bonding with another substrate by molecular bonding, perform the bonding, the other substrate being the said support substrate made of an insulating material, eliminate all or part of the wafer of semiconducting material.

摘要翻译： 本发明涉及一种用于制造一种电子结构的方法，该电子结构包括至少一种活性组分和由绝缘材料制成的支撑衬底上的至少一种无源组件或元件。 特征性方法包括以下步骤：使活性组分由包含支撑所述表面层的半导体材料晶片的初始衬底制成由半导体材料制成的表面层，使得能够将被动元件或元件与 使被动部件或元件在电绝缘区域上和/或电绝缘区域中，利用所述电子结构准备初始基板面的表面，以使该表面与通过分子键合与另一基板结合，进行粘合， 另一个衬底是由绝缘材料制成的所述支撑衬底，消除半导体材料的全部或部分晶片。

公开(公告)号：US5373462A

公开(公告)日：1994-12-13

申请号：US17750

申请日：1993-02-16

申请人： Herve Achard ,  Jean-Pierre Joly

发明人： Herve Achard ,  Jean-Pierre Joly

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/223

摘要： A process for producing an improved non-volatile storage cell of the metal-ferroelectric-semiconductor type is provided. The non-volatile storage cell has at least one metal-ferroelectric-semiconductor transistor formed in a semiconductor substrate and having a source (5), a drain (6), and a gate (4). The gate is insulated from the source and the drain by a ferroelectric layer (2). The transistor has at least one lateral programming electrode (BL) in contact with the ferroelectric layer and insulated from the gate. In a preferred embodiment the cell also has a dielectric layer (7) interposed between the ferroelectric layer and the substrate. Particular utility for the present invention is found in the area of static memory devices, although other utilities are contemplated.

摘要翻译： 提供了一种用于制造金属 - 铁电 - 半导体型改进的非易失性存储单元的方法。 非易失性存储单元具有至少一个形成在半导体衬底中并具有源极（5），漏极（6）和栅极（4）的金属 - 铁电半导体晶体管。 栅极通过铁电层（2）与源极和漏极绝缘。 晶体管具有与铁电层接触并与栅极绝缘的至少一个横向编程电极（BL）。 在优选实施例中，电池还具有置于铁电层和衬底之间的电介质层（7）。 尽管可以考虑其他实用方案，但是在静态存储器件的领域中发现了本发明的特别实用性。

公开(公告)号：US20050258489A9

公开(公告)日：2005-11-24

申请号：US10928057

申请日：2004-06-02

申请人： Jean-Pierre Joly ,  Michel Bruel ,  Claude Jaussaud

发明人： Jean-Pierre Joly ,  Michel Bruel ,  Claude Jaussaud

IPC分类号： H01L21/762 ,  H01L23/373 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/76251 ,  H01L23/3735 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

摘要翻译： 本发明涉及一种薄层半导体结构，其包括通过中间区（3）从支撑衬底（1）分离的半导体表面层（2），所述中间区（3）是多层电绝缘的 半导体表面层从支撑基底。 中间区域具有与半导体表面层的界面充分良好的电气质量，并且包括至少一个具有令人满意的导热性的第一层，以提供将要被阐述的电子设备或设备的正确操作 所述半导体表面层（2），所述中间区域另外包括位于所述第一层和所述支撑衬底之间的低介电常数的第二绝缘层。