公开(公告)号：US20050196955A1

公开(公告)日：2005-09-08

申请号：US11114563

申请日：2005-04-25

Applicant: Ting Tsui ,  Andrew McKerrow ,  Jeannette Jacques

Inventor： Ting Tsui ,  Andrew McKerrow ,  Jeannette Jacques

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/4763

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides an insulating layer 100 for an integrated circuit 110 comprising a porous silicon-based dielectric layer 120 located over a substrate 130. The insulating layer comprises a densified layer 140 comprising an uppermost portion 142 of the porous silicon-based dielectric layer.

Abstract translation: 本发明提供了一种用于集成电路110的绝缘层100，其包括位于衬底130上方的多孔硅基电介质层120。 绝缘层包括致密层140，其包括多孔硅基电介质层的最上部分142。

公开(公告)号：US20070042599A1

公开(公告)日：2007-02-22

申请号：US11207493

申请日：2005-08-19

Applicant: Ting Tsui ,  Jeannette Jacques ,  Robert Kraft ,  Ping Jiang

Inventor： Ting Tsui ,  Jeannette Jacques ,  Robert Kraft ,  Ping Jiang

IPC: H01L21/4763

CPC classification number: H01L21/76825 ,  H01L21/76807

Abstract: A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

Abstract translation: 用基于能量的工艺制造半导体器件，其改变镶嵌工艺内的电介质层的蚀刻速率。 第一互连层形成在半导体本体上。 第一介电层形成在第一互连层上。 改变第一介电层的蚀刻速率。 在第一电介质层上形成第二电介质层。 然后改变第二电介质层的蚀刻速率。 执行沟槽蚀刻以在第二介电层内形成沟槽。 执行通孔蚀刻以在第一介电层内形成通孔腔。 空腔填充有导电材料，然后平坦化以除去多余的填充材料。