公开(公告)号：US20050263795A1

公开(公告)日：2005-12-01

申请号：US11137608

申请日：2005-05-24

申请人： Jeong-Dong Choi ,  Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim

发明人： Jeong-Dong Choi ,  Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim

IPC分类号： H01L29/78 ,  H01L21/335 ,  H01L21/336 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/78687 ,  H01L29/66795 ,  H01L29/785

摘要： In a method of forming a semiconductor device having an improved channel layer, the channel layer is formed on a surface of a semiconductor substrate and comprises a material of high carrier mobility such as silicon germanium (SiGe), germanium (Ge) and silicon carbide (SiC) using a selective epitaxial growth process. A gate insulation layer and a gate electrode are formed on the channel layer. Accordingly, a driving current of the semiconductor device increases to thereby improve operation characteristics.

摘要翻译： 在形成具有改进的沟道层的半导体器件的方法中，沟道层形成在半导体衬底的表面上，并且包括诸如硅锗（SiGe），锗（Ge）和碳化硅的高载流子迁移率的材料 SiC），使用选择性外延生长工艺。 栅极绝缘层和栅电极形成在沟道层上。 因此，半导体器件的驱动电流增加，从而改善操作特性。

公开(公告)号：US06875666B2

公开(公告)日：2005-04-05

申请号：US10458028

申请日：2003-06-09

申请人： Chang-Sub Lee ,  Jeong-Dong Choi ,  Seong-Ho Kim ,  Shin-Ae Lee ,  Sung-Min Kim ,  Dong-Gun Park

发明人： Chang-Sub Lee ,  Jeong-Dong Choi ,  Seong-Ho Kim ,  Shin-Ae Lee ,  Sung-Min Kim ,  Dong-Gun Park

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/10

CPC分类号： H01L27/10873 ,  H01L21/26586 ,  H01L21/823412 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/1083

摘要： Transistors of a semiconductor device are fabricated by forming a plurality of gate electrodes on a semiconductor substrate. The gate electrodes are used as an ion implantation mask. A first impurity is ion implanted below the exposed surface of the semiconductor substrate to form first impurity regions. A second impurity is ion implanted in two directions by tilting the implantation to a predetermined angle to thereby form second impurity regions separated from the first impurity regions. The second impurity regions are formed below the channel region under the gate electrodes. The second impurity regions may overlap to provide a higher impurity concentration below a portion of the channel.

摘要翻译： 通过在半导体衬底上形成多个栅电极来制造半导体器件的晶体管。 栅电极用作离子注入掩模。 第一杂质是离子注入到半导体衬底的暴露表面之下以形成第一杂质区。 通过将注入倾斜到预定角度从而将第二杂质离子注入两个方向，从而形成与第一杂质区分离的第二杂质区。 第二杂质区形成在栅极下方的沟道区的下方。 第二杂质区域可以重叠，以在通道的一部分下方提供较高的杂质浓度。