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公开(公告)号：US6026003A
公开(公告)日：2000-02-15
申请号：US215932
申请日：1998-12-18
CPC分类号： H02M3/073 , H02M2003/078
摘要： A charge pump (102) and method of charge pumping a low voltage (V.sub.DD)) to generate a higher voltage (V.sub.PP). A primary pump (160, 179, 180) receives complementary clock signals (CLK1, CLK2) that control charging and transfer cycles of the charge pump. During the charging cycle, a capacitor (150) stores a charge developed from the low voltage. On the transfer cycle, the charge is transferred to an output (138, 177, 178) through a switching transistor (152) disposed in a well region (202) to develop the higher voltage. A secondary pump (162, 187, 188) charge pumps the output voltage to generate a more positive bias voltage for biasing the well region to disable a parasitic PNP transistor of the switching transistor.
摘要翻译： 电荷泵（102）和电荷泵浦低电压（VDD）的方法）以产生较高电压（VPP）。 主泵（160,179,180）接收控制电荷泵的充电和传送周期的互补时钟信号（CLK1，CLK2）。 在充电循环期间，电容器（150）存储从低电压产生的电荷。 在传送周期中，通过布置在阱区（202）中的开关晶体管（152）将电荷转移到输出端（138,177,178）以产生较高的电压。 二次泵（162,187,188）对输出电压进行泵浦以产生更正的偏置电压，以偏置阱区以禁用开关晶体管的寄生PNP晶体管。
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公开(公告)号：US5898633A
公开(公告)日：1999-04-27
申请号：US859897
申请日：1997-05-21
IPC分类号： H01L27/04 , G11C16/30 , H01L21/822 , G11C8/00
CPC分类号： G11C16/30
摘要： A current limiting circuit (70) controls the leakage current of a memory circuit (24) of a portable wireless device (10) while operating in a standby mode. A first semiconductor well (64) isolates the memory circuit (24) that is disposed in a second semiconductor well (66) from a substrate (62). In the standby mode the current limiting circuit (70) is switched to a non-conduction mode that limits the leakage currents of a diode formed by the first semiconductor well (66) with the second semiconductor well (64) and a diode formed by the second semiconductor well (64) with the substrate (62).
摘要翻译： 当处于待机模式时，限流电路（70）控制便携式无线设备（10）的存储电路（24）的漏电流。 第一半导体阱（64）将设置在第二半导体阱（66）中的存储电路（24）与衬底（62）隔离。 在待机模式中，限流电路（70）切换到非导通模式，其限制由第一半导体阱（66）与第二半导体阱（64）形成的二极管的漏电流和由 第二半导体阱（64）与衬底（62）。
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公开(公告)号：US06747494B2
公开(公告)日：2004-06-08
申请号：US10077467
申请日：2002-02-15
IPC分类号： H03L706
CPC分类号： H03L7/0895
摘要： A charge pump arrangement for a phase-locked-loop has a current source circuit (60) which provides charging current to the phase locked loop, and a current sink circuit (90) which depletes charging current from the phase locked loop. The current source circuit (60) and the current sink circuit (90) have slew rates which have a predetermined relationship. In this way, the charge pump causes substantially no non-linear charge injection in the phase-locked-loop. Cascoded current mirrors (75, 85) are utilised to provide a high voltage with thin gate oxide technology. The arrangement has a relatively small die size. Since bias currents of the arrangement are mirrored according to the output current required, improved transient times are produced, leading to reduced phase noise.
摘要翻译： 用于锁相环的电荷泵装置具有向锁相环提供充电电流的电流源电路（60）和从锁相环消耗充电电流的电流吸收电路（90）。 电流源电路（60）和电流吸收电路（90）具有预定关系的转换速率。 以这种方式，电荷泵在锁相环中基本上不引起非线性电荷注入。 Cascoded电流镜（75,85）用于提供具有薄栅极氧化物技术的高电压。 该布置具有相对较小的管芯尺寸。 由于该装置的偏置电流根据所需的输出电流进行镜像，因此产生改善的瞬态时间，导致相位噪声的降低。
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4.发明授权
公开(公告)号：US6041221A
公开(公告)日：2000-03-21
申请号：US859898
申请日：1997-05-21
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A memory circuit (24) limits the threshold voltage distribution for either programming or erasing a memory cell (40A) in a non-volatile memory array (34). A data latch (90) provides a current (I.sub.REF) to the memory cell (40A) that increases in current as the operating temperature of the memory cells (40A, 40B) increases. Current generated by the data latch (90) increases when the processing parameters cause a greater conductivity of the transistors in the memory cell (40A) and the current decreases when the processing parameters cause a lesser conductivity of the transistors in the memory cell (40A), thus allowing narrower limits on the distribution of the program and erase threshold voltages.
摘要翻译： 存储器电路（24）限制用于编程或擦除非易失性存储器阵列（34）中的存储器单元（40A）的阈值电压分布。 当存储器单元（40A，40B）的工作温度升高时，数据锁存器（90）向存储器单元（40A）提供电流（IREF），其随着电流的增加而增加。 当处理参数导致存储单元（40A）中的晶体管的较大导电性并且当处理参数导致存储单元（40A）中的晶体管的较小导电性时，电流减小，由数据锁存器（90）产生的电流增加， ，从而允许对编程分布的较窄限制和擦除阈值电压。
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公开(公告)号：US5828607A
公开(公告)日：1998-10-27
申请号：US861078
申请日：1997-05-21
摘要： A circuit and method modify data stored in a storage element (30) of a memory circuit (110) when high voltages used for such modification exceed transistor breakdowns. A charge pump (302) produces a pumped voltage (V.sub.P1) for modifying the data. A monitor circuit (304) produces an enable signal (V.sub.PEN) to activate other power supply voltages when the pumped voltage reaches a predetermined voltage level for allowing the data to be modified. A routing circuit (832) selects between the pumped voltage and a first voltage (V.sub.DD) in response to a first control signal (HVENABLEP) to produce a selected voltage. A switching circuit (802-808) passes the selected voltage to the storage element (30) to modify the data when the first supply voltage is selected by the routing circuit.
摘要翻译： 当用于这种修改的高电压超过晶体管故障时，电路和方法修改存储在存储电路（110）的存储元件（30）中的数据。 电荷泵（302）产生用于修改数据的泵浦电压（VP1）。 当泵浦电压达到预定电压电平以允许数据被修改时，监视器电路（304）产生使能信号（VPEN）以激活其它电源电压。 路由电路（832）响应于第一控制信号（HVENABLEP）在泵浦电压和第一电压（VDD）之间选择以产生所选择的电压。 当由路由电路选择第一电源电压时，开关电路（802-808）将所选择的电压传递到存储元件（30）以修改数据。
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公开(公告)号：US5754010A
公开(公告)日：1998-05-19
申请号：US859963
申请日：1997-05-21
摘要： A memory circuit (24) includes a sense amp circuit (30) that uses multiplexers (86) in a column mux (32) for pre-charging only selected bitlines in order to limit the current during a read operation of the FLASH memory circuit (24). The sense amp circuit (30) provides the bitline with a pre-charge voltage that is set by a current reference (68) that is substantially supply independent. In the read mode the sense amp circuit (30) responds to either a voltage on the bitline that is lowered from the pre-charge voltage value by a selected programmed memory cell (40) or by a voltage that remains at the pre-charged voltage value for an unprogrammed memory cell.
摘要翻译： 存储器电路（24）包括读出放大器电路（30），该读出放大器电路使用列复用器（32）中的多路复用器（86）来仅预选所选择的位线，以便在闪速存储器电路的读取操作期间限制电流 24）。 感测放大器电路（30）为位线提供由基本上独立供电的电流基准（68）设置的预充电电压。 在读取模式下，感测放大器电路（30）响应来自预充电电压值的位线上的电压由选择的编程存储器单元（40）或保持在预充电电压 未编程存储单元的值。
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公开(公告)号：US5953251A
公开(公告)日：1999-09-14
申请号：US215933
申请日：1998-12-18
CPC分类号： G11C16/10
摘要： A programming method for a floating gate memory circuit (100) includes a block erase (step 81) in which a first programming signal is applied to memory cells of a selected block of the memory to store a first value of charge in the memory cells of the block. Data is programmed by applying a second programming signal to a first memory cell to store a second value in the first memory cell (step 83). A third programming signal is applied to a second memory cell to write a correction charge that compensates for a change in the first value of charge induced by the second programming signal (step 84).
摘要翻译： 用于浮动栅极存储器电路（100）的编程方法包括块擦除（步骤81），其中第一编程信号被施加到存储器的选定块的存储器单元，以将第一电荷值存储在存储器单元的存储器单元中 块。 通过将第二编程信号施加到第一存储器单元以将第二值存储在第一存储器单元中来编程数据（步骤83）。 第三编程信号被施加到第二存储器单元以写入补偿由第二编程信号引起的电荷的第一值的变化的校正电荷（步骤84）。
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