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1.发明授权Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels 有权通过可配置的字线电压电平实现增强的SRAM稳定性和增强的芯片产量公开(公告)号：US07911827B2
公开(公告)日：2011-03-22
申请号：US12360242
申请日：2009-01-27
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C11/41 , G11C11/413 , G11C11/419 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/5002
摘要： An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.
摘要翻译： 一种内置自检（ABIST）方法的阵列和用于使用可配置字线电压电平实现增强型静态随机存取存储器（SRAM）稳定性和增强的芯片产量的电路，以及提供主题电路所在的设计结构。 字线连接到SRAM存储单元。 多个字线电压下拉器件连接到字线。 相应的字线电压控制输入信号被施加到多个字线电压下拉器件中的每一个以选择性地调节字线的电压电平。
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公开(公告)号：US07844869B2
公开(公告)日：2010-11-30
申请号：US12015254
申请日：2008-01-16
IPC分类号： G01R31/28
CPC分类号： G01R31/3187
摘要： A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.
摘要翻译： 一种包括存储器阵列和逻辑的电路路径的方法和电路实现测试，包括逻辑内置自测（LBIST）诊断，以及提供了主题电路所在的设计结构。 电路路径的测试包括用初始化模式初始化电路路径中的存储器阵列，切换到逻辑内置自测（LBIST）模式，并为存储器阵列提供只读模式，并运行逻辑内置自检（LBIST） ）测试电路路径。
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3.发明申请Implementing Enhanced Array Access Time Tracking With Logic Built in Self Test of Dynamic Memory and Random Logic 有权实现增强的阵列访问时间跟踪逻辑内置动态内存和随机逻辑的自检公开(公告)号：US20100218055A1
公开(公告)日：2010-08-26
申请号：US12393156
申请日：2009-02-26
IPC分类号： G06F11/00
CPC分类号： G11C29/14 , G11C29/50012
摘要： A method and circuit for implementing substantially perfect array access time tracking with Logic Built In Self Test (LBIST) diagnostics of dynamic memory array and random logic, and a design structure on which the subject circuit resides are provided. The dynamic memory array is initialized to a state for the longest read time for each bit and the dynamic memory array is forced into a read only mode. During LBIST diagnostics with the array in the read only mode, the array outputs are combined with the data inputs to provide random switching data on the array outputs to the random logic.
摘要翻译： 用于通过动态存储器阵列和随机逻辑的逻辑内置自检（LBIST）诊断以及提供主题电路所在的设计结构来实现基本上完美的阵列访问时间跟踪的方法和电路。 动态存储器阵列被初始化为每个位最长读取时间的状态，并且动态存储器阵列被强制进入只读模式。 在采用只读模式的阵列LBIST诊断期间，阵列输出与数据输入相结合，为阵列输出提供随机逻辑的随机数据。
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4.发明授权Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability 失效实现本地评估多米诺骨牌SRAM，增强SRAM单元的稳定性公开(公告)号：US07724585B2
公开(公告)日：2010-05-25
申请号：US12195117
申请日：2008-08-20
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.
摘要翻译： 一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。 能够对相关联的SRAM单元组进行读和写操作的SRAM本地评估电路包括真实和补码位线，单个写入数据传播输入，预充电信号和预充电写入信号。 传递门装置连接在补码位线和写入数据传播输入之间。 晶体管堆叠与真正位线和地之间的预充电装置串联连接。 在读取操作期间，预充电写入信号禁止连接在补码位线和写入数据传播输入之间的通道器件。 在写操作期间，预充电写入信号使得连接在补码位线和写入数据传播输入之间的通道器件能够激活晶体管堆叠。
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5.发明授权Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic 有权实现增强的阵列访问时间跟踪，内置动态内存和随机逻辑的自检逻辑公开(公告)号：US07925950B2
公开(公告)日：2011-04-12
申请号：US12393156
申请日：2009-02-26
IPC分类号： G01R31/28
CPC分类号： G11C29/14 , G11C29/50012
摘要： A method and circuit for implementing substantially perfect array access time tracking with Logic Built In Self Test (LBIST) diagnostics of dynamic memory array and random logic, and a design structure on which the subject circuit resides are provided. The dynamic memory array is initialized to a state for the longest read time for each bit and the dynamic memory array is forced into a read only mode. During LBIST diagnostics with the array in the read only mode, the array outputs are combined with the data inputs to provide random switching data on the array outputs to the random logic.
摘要翻译： 用于通过动态存储器阵列和随机逻辑的逻辑内置自检（LBIST）诊断以及提供主题电路所在的设计结构来实现基本上完美的阵列访问时间跟踪的方法和电路。 动态存储器阵列被初始化为每个位最长读取时间的状态，并且动态存储器阵列被强制进入只读模式。 在采用只读模式的阵列LBIST诊断期间，阵列输出与数据输入相结合，为阵列输出提供随机逻辑的随机数据。
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6.发明授权Low power level shifting latch circuits with gated feedback for high speed integrated circuits 失效低功率电平移位锁存电路，具有门控反馈用于高速集成电路公开(公告)号：US07737757B2
公开(公告)日：2010-06-15
申请号：US12178071
申请日：2008-07-23
IPC分类号： H03K19/0175
CPC分类号： H03K3/356121
摘要： Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.
摘要翻译： 具有用于高速集成电路的门控反馈的低功率电平移位器锁存电路，以及设有主题电路所在的设计结构。 操作在第一电压源的域中的锁存器输入级接收响应于通过预定时钟信号使能的数据输入。 耦合到锁存器输入级的锁存器存储元件包括在第二电压源的区域中操作的锁存器输出级提供具有与第二电压源相对应的电压电平的数据输出。 闩锁存储元件包括电平移位装置，其提供从第一电源电平到第二电压供应电平的电平移位。 锁存器存储元件包括反馈栅极器件，当数据被写入锁存器输入级时，反馈栅极器件接收预定义的时钟信号以对门锁反馈到锁存器输入级。
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7.发明申请Implementing Enhanced SRAM Stability and Enhanced Chip Yield With Configurable Wordline Voltage Levels 有权通过可配置的字线电压电平实现增强的SRAM稳定性和增强的芯片产量公开(公告)号：US20100188886A1
公开(公告)日：2010-07-29
申请号：US12360242
申请日：2009-01-27
CPC分类号： G11C8/08 , G11C11/41 , G11C11/413 , G11C11/419 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/5002
摘要： An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.
摘要翻译： 一种内置自检（ABIST）方法的阵列和用于使用可配置字线电压电平实现增强型静态随机存取存储器（SRAM）稳定性和增强的芯片产量的电路，以及提供主题电路所在的设计结构。 字线连接到SRAM存储单元。 多个字线电压下拉器件连接到字线。 相应的字线电压控制输入信号被施加到多个字线电压下拉器件中的每一个以选择性地调节字线的电压电平。
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8.发明申请Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability 失效实现具有增强的SRAM单元稳定性的Domino读取SRAM的本地评估公开(公告)号：US20100046277A1
公开(公告)日：2010-02-25
申请号：US12195117
申请日：2008-08-20
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.
摘要翻译： 一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。 能够对相关联的SRAM单元组进行读和写操作的SRAM本地评估电路包括真实和补码位线，单个写入数据传播输入，预充电信号和预充电写入信号。 传递门装置连接在补码位线和写入数据传播输入之间。 晶体管堆叠与真正位线和地之间的预充电装置串联连接。 在读取操作期间，预充电写入信号禁止连接在补码位线和写入数据传播输入之间的通道器件。 在写操作期间，预充电写入信号使得连接在补码位线和写入数据传播输入之间的通道器件能够激活晶体管堆叠。
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9.发明申请Low Power Level Shifting Latch Circuits With Gated Feedback for High Speed Integrated Circuits 失效具有门控反馈的低功率电平移位锁存电路用于高速集成电路公开(公告)号：US20100019824A1
公开(公告)日：2010-01-28
申请号：US12178071
申请日：2008-07-23
IPC分类号： H03L5/00
CPC分类号： H03K3/356121
摘要： Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.
摘要翻译： 具有用于高速集成电路的门控反馈的低功率电平移位器锁存电路，以及设有主题电路所在的设计结构。 操作在第一电压源的域中的锁存器输入级接收响应于通过预定时钟信号使能的数据输入。 耦合到锁存器输入级的锁存器存储元件包括在第二电压源的区域中操作的锁存器输出级提供具有与第二电压源相对应的电压电平的数据输出。 闩锁存储元件包括电平移位装置，其提供从第一电源电平到第二电压供应电平的电平移位。 锁存器存储元件包括反馈栅极器件，当数据被写入锁存器输入级时，反馈栅极器件接收预定义的时钟信号以对门锁反馈到锁存器输入级。
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10.发明申请Method and circuit for implementing enhanced LBIST testing of paths including arrays 有权用于实现包括阵列的路径的增强型LBIST测试的方法和电路公开(公告)号：US20090183044A1
公开(公告)日：2009-07-16
申请号：US12015254
申请日：2008-01-16
IPC分类号： G01R31/3187 , G06F11/27
CPC分类号： G01R31/3187
摘要： A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.
摘要翻译： 一种包括存储器阵列和逻辑的电路路径的方法和电路实现测试，包括逻辑内置自测（LBIST）诊断，以及提供了主题电路所在的设计结构。 电路路径的测试包括用初始化模式初始化电路路径中的存储器阵列，切换到逻辑内置自测（LBIST）模式，并为存储器阵列提供只读模式，并运行逻辑内置自检（LBIST） ）测试电路路径。
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