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    Process for improving the reliability of interconnect structures and resulting structure
    1.
    发明授权
    Process for improving the reliability of interconnect structures and resulting structure 有权
    提高互连结构和结构结构可靠性的方法

    公开(公告)号：US07816256B2

    公开(公告)日：2010-10-19

    申请号：US11487741

    申请日：2006-07-17

    Applicant: Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

    Inventor： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

    IPC: H01L21/4763

    CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

    Abstract translation: 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

    Process for Improving the Reliability of Interconnect Structures and Resulting Structure
    5.
    发明申请
    Process for Improving the Reliability of Interconnect Structures and Resulting Structure 有权
    提高互连结构和结构结构可靠性的过程

    公开(公告)号：US20100327456A1

    公开(公告)日：2010-12-30

    申请号：US12879770

    申请日：2010-09-10

    Applicant: Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

    Inventor： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

    IPC: H01L23/52

    CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

    Abstract translation: 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

    Photomask cleaning using vacuum ultraviolet (VUV) light cleaning
    6.
    发明申请
    Photomask cleaning using vacuum ultraviolet (VUV) light cleaning 审中-公开
    使用真空紫外线（VUV）清洁光掩模

    公开(公告)号：US20070012335A1

    公开(公告)日：2007-01-18

    申请号：US11184703

    申请日：2005-07-18

    Applicant: Hsiao Chang ,  Tsun-Cheng Tang ,  Fei-Gwo Tsai ,  Tzu-Li Lee ,  Chien-Ming Chiu ,  Jang Lee ,  Yih-Chen Su ,  Chih-Cheng Lin ,  Tung Kang ,  Hung Hsieh

    Inventor： Hsiao Chang ,  Tsun-Cheng Tang ,  Fei-Gwo Tsai ,  Tzu-Li Lee ,  Chien-Ming Chiu ,  Jang Lee ,  Yih-Chen Su ,  Chih-Cheng Lin ,  Tung Kang ,  Hung Hsieh

    IPC: B08B3/12 ,  B08B3/00 ,  B08B6/00

    CPC classification number: B08B7/0035 ,  B08B3/08 ,  B08B7/0042 ,  B08B7/0071 ,  G03F1/82

    Abstract: A multi-step cleaning procedure cleans phase shift photomasks and other photomasks and Mo-containing surfaces. In one embodiment, vacuum ultraviolet (VUV) light produced by an Xe2 excimer laser converts oxygen to ozone that is used in a first cleaning operation. The VUV/ozone clean may be followed by a wet SC1 chemical clean and the two-step cleaning procedure reduces phase-shift loss and increases transmission. In another embodiment, the first step may use other means to form a molybdenum oxide on the Mo-containing surface. In another embodiment, the multi-step cleaning operation provides a wet chemical clean such as SC1 or SPM or both, followed by a further chemical or physical treatment such as ozone, baking or electrically ionized water.

    Abstract translation: 多步清洁程序可以清洗相移光掩模和其他光掩模和含Mo表面。 在一个实施方案中，由Xe 2激子准分子激光器产生的真空紫外线（VUV）光将氧气转化为在第一清洁操作中使用的臭氧。 VUV /臭氧清洁后可以进行湿式SC1化学清洗，两步清洗程序可以减少相移损失并增加透光率。 在另一个实施方案中，第一步可以使用其它方法在含Mo表面上形成氧化钼。 在另一个实施方案中，多步骤清洁操作提供湿化学清洁例如SC1或SPM或两者，随后进一步进行化学或物理处理，例如臭氧，烘烤或电离水。

    Method for forming semiconductor structure having protection layer for preventing laser damage
    8.
    发明授权
    Method for forming semiconductor structure having protection layer for preventing laser damage 有权
    用于形成具有用于防止激光损伤的保护层的半导体结构的方法

    公开(公告)号：US08541264B2

    公开(公告)日：2013-09-24

    申请号：US13548039

    申请日：2012-07-12

    Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

    Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

    IPC: H01L21/82

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

    Abstract translation: 提供一种用于形成半导体结构的方法，以防止用于吹送形成在半导体衬底上的金属层上的至少一个熔丝的能量引起对结构的损坏。 半导体结构包括器件，保护环，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

    PROTECTION LAYER FOR PREVENTING LASER DAMAGE ON SEMICONDUCTOR DEVICES
    9.
    发明申请
    PROTECTION LAYER FOR PREVENTING LASER DAMAGE ON SEMICONDUCTOR DEVICES 有权
    用于防止半导体器件激光损伤的保护层

    公开(公告)号：US20120276732A1

    公开(公告)日：2012-11-01

    申请号：US13548039

    申请日：2012-07-12

    Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

    Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

    IPC: H01L21/768

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

    Abstract translation: 提供一种用于形成半导体结构的方法，以防止用于吹送形成在半导体衬底上的金属层上的至少一个熔丝的能量引起对结构的损坏。 半导体结构包括器件，保护环，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

    Process for improving the reliability of interconnect structures and resulting structure
    10.
    发明授权
    Process for improving the reliability of interconnect structures and resulting structure 有权
    提高互连结构和结构结构可靠性的方法

    公开(公告)号：US08212330B2

    公开(公告)日：2012-07-03

    申请号：US12879770

    申请日：2010-09-10

    Applicant: Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

    Inventor： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

    IPC: H01L23/52

    CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

    Abstract translation: 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

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