公开(公告)号：US07305595B2

公开(公告)日：2007-12-04

申请号：US10660006

申请日：2003-09-11

申请人： Joel Gerard Goodwin ,  Manish Misra ,  John Daniel Upton

发明人： Joel Gerard Goodwin ,  Manish Misra ,  John Daniel Upton

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G01R31/318533 ,  G01R31/318597 ,  G11C5/04 ,  G11C29/56008 ,  G11C2029/0409

摘要： A method, system, and product are disclosed for isolating a defect in a memory system by determining in which particular component of the memory system the defect exists. The memory system includes multiple components. The components include a physical memory module, a memory card to which the physical memory module is attached, and a memory controller for controlling the memory card. The memory card includes one or more electrical buffers for driving or detecting the memory signals. The buffers may be used as virtual memory elements. Each component is tested separately in order to identify the defective component with the help of virtual memory system elements. The components are tested by first testing the physical memory module. If the physical memory module passes the test, the memory card is then tested. If the memory card passes its test, the memory controller is tested.

摘要翻译： 公开了一种方法，系统和产品，用于通过确定存储系统的哪个特定部件存在缺陷来隔离存储器系统中的缺陷。 存储器系统包括多个组件。 这些组件包括物理存储器模块，物理存储器模块所连接的存储卡，以及用于控制存储卡的存储器控​​制器。 存储卡包括用于驱动或检测存储器信号的一个或多个电气缓冲器。 缓冲器可以用作虚拟存储器元件。 每个组件都被单独测试，以便借助虚拟内存系统元素识别有缺陷的组件。 通过首先测试物理内存模块来测试组件。 如果物理内存模块通过测试，则会对存储卡进行测试。 如果存储卡通过其测试，则对存储器控制器进行测试。

公开(公告)号：US06218966B1

公开(公告)日：2001-04-17

申请号：US09187072

申请日：1998-11-05

申请人： Joel Gerard Goodwin ,  Scott Harlan Isensee ,  Ricky Lee Poston ,  I-hsing Tsao

发明人： Joel Gerard Goodwin ,  Scott Harlan Isensee ,  Ricky Lee Poston ,  I-hsing Tsao

IPC分类号： H03M1100

CPC分类号： G06F3/016 ,  G06F3/0202

摘要： A key assembly includes a cover disposed over a transducer which is connected to a key acutator/interface disposed between the key transducer and a CPU. A tactile signal generator generates control signals from the CPU to activate the actuator/interface. The actuator/interface provides a signal appropriate to the particular transducer causing it to produce tactile feedback response to the key cover and user's touch. The key assembly may include a larger key cover disposed over a plurality of key transducers whereby the CPU causes texture and fine detail sensations variable over the key cover area by selective, variable actuation of the transducers. The end-user may thereby sense by physical contact with the large key cover electronically generated sensations of irregular surfaces or textures. Tactile profiles either user-specified or automatically invoked by a corresponding application vary the keyboard touch and feel as defined by the selected profile.

摘要翻译： 钥匙组件包括设置在换能器上的盖，该盖连接到设置在钥匙换能器和CPU之间的按键辅助器/接口。 触觉信号发生器产生来自CPU的控制信号以激活致动器/接口。 致动器/接口提供适合于特定换能器的信号，使其产生对键盖和用户触摸的触觉反馈响应。 钥匙组件可以包括设置在多个钥匙换能器上的较大的钥匙盖，由此CPU通过选择性地，可变地致动换能器而使钥匙盖区域上的纹理和细小的细节感觉变化。 因此，最终用户可以通过与大键盖的电子产生的不规则表面或纹理感觉的物理接触来感测。 用户指定或由相应应用程序自动调用的触觉配置会改变所选配置文件所定义的键盘触摸和感觉。

公开(公告)号：US07085863B2

公开(公告)日：2006-08-01

申请号：US10698065

申请日：2003-10-30

申请人： Michael Anton Barenys ,  Stephan Otis Broyles ,  Robert Allan Faust ,  Joel Gerard Goodwin

发明人： Michael Anton Barenys ,  Stephan Otis Broyles ,  Robert Allan Faust ,  Joel Gerard Goodwin

IPC分类号： G06F13/00 ,  G06F11/07

CPC分类号： G06F13/4286

摘要： An I2C device is disclosed that includes a main I2C section, bus switches, switch logic, and address logic as part of the I2C device. The I2C device is coupled to an I2C bus for communicating with other I2C devices and an I2C bus controller that is also on the I2C bus. The switch logic controls a current position of the switches. The I2C device is coupled to the I2C bus utilizing the switches. The switches control whether the main I2C section, the address logic, the switch logic, or a combination of the main I2C section, address logic, and switch logic is currently coupled to I2C bus. The switches also can be used, if desired to remove from the buss all devices that are downstream from a given device containing switches. The address logic is used to receive and store the address of the I2C device. The I2C device will respond to the address that is stored in its address logic.

摘要翻译： 公开了一种包括主I 2 C部分，总线开关，开关逻辑和作为I 2 2 C部分的地址逻辑的I < SUP> C设备。 I 2 C装置耦合到I 2 C总线，用于与其他I 2 C装置通信，以及I < / SUP> C总线控制器，也在I ^{2 C总线上。 开关逻辑控制开关的当前位置。 使用开关将I 2 SUPER C装置耦合到I 2 C总线。 开关控制主I 2 S区段，地址逻辑，开关逻辑或主I 2 SUP区段，地址逻辑和开关逻辑的组合 目前与I C> C总线相连。 如果需要从交换机的给定设备下游的所有设备中删除所有设备，也可以使用交换机。 地址逻辑用于接收和存储I 2 C设备的地址。 I 2 C设备将响应存储在其地址逻辑中的地址。}

公开(公告)号：US06976197B2

公开(公告)日：2005-12-13

申请号：US09999663

申请日：2001-10-25

申请人： Robert Allan Faust ,  Joel Gerard Goodwin

发明人： Robert Allan Faust ,  Joel Gerard Goodwin

IPC分类号： G06F11/10 ,  G11C29/00

CPC分类号： G06F11/1048 ,  G11C2029/1208

摘要： An apparatus and method for error logging on a memory module, such as a DIMM, are provided. If an error occurs in a memory module, the operating system of the computing device stores a log of the error in a storage device mounted to the memory module. The log may identify the type and quantity of errors caused by the faulty memory module and may also include defective bit identification information. The defective bit identification information may be used to identify individual memory elements on the memory module that are defective. If the errors exceed a given quality or quantity level, the operating system may store an indicator in the storage device on the memory module that the memory module is defective and take that memory module off-line to prevent problems from occurring with the programs that are running on the computing system.

摘要翻译： 提供了用于错误登录在诸如DIMM的存储器模块上的装置和方法。 如果内存模块发生错误，则计算设备的操作系统将错误的日志存储在安装到内存模块的存储设备中。 日志可以识别由故障存储器模块引起的错误的类型和数量，并且还可以包括有缺陷的位识别信息。 有缺陷的位识别信息可用于识别存储器模块中的有缺陷的各个存储元件。 如果错误超出给定的质量或数量级别，则操作系统可以将存储器模块中的存储设备中的指示符存储在存储器模块有缺陷的位置，并将该存储器模块脱机，以防止出现与所述程序相关的问题 运行在计算系统上。

公开(公告)号：US06622188B1

公开(公告)日：2003-09-16

申请号：US09163992

申请日：1998-09-30

申请人： Joel Gerard Goodwin ,  Steven Paul Hartman ,  Scott Harlan Isensee ,  Wally Tuten

发明人： Joel Gerard Goodwin ,  Steven Paul Hartman ,  Scott Harlan Isensee ,  Wally Tuten

IPC分类号： G06F1100

CPC分类号： G06F13/4045

摘要： An apparatus and method for expansion of an inter-IC (I2C) is provided. An expansion processor resides on a primary I2C bus. The expansion processor is coupled to a plurality of I2C sub-buses each of which may host a plurality of I2C devices. Data is transferred between the expansion processor and the plurality of I2C devices via the corresponding sub-bus according to an I2C protocol. Data transfer is in response to a request initiated by a bus master on the primary I2C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which the echos it to the target device. Likewise, a data stream bound from the target device to the bus master on the primary I2C bus is transmitted to the expansion processor which the echos it to the bus master.

摘要翻译： 提供了一种用于扩展IC（I2C）的装置和方法。 扩展处理器驻留在主I2C总线上。 扩展处理器耦合到多个I2C子总线，每个子副总线可以承载多个I2C设备。 根据I2C协议，数据通过相应的副总线在扩展处理器和多个I2C设备之间传输。 数据传输是响应由主I2C总线上的总线主机发起的请求。 总线主机通过寻址扩展处理器与位于其中一个子总线上的目标设备进行通信。 总线主机通过向扩展处理器发送目标设备所在的子总线数目和目标设备的地址来通知目标设备的扩展处理器。 绑定到目标设备的数据流被引导到扩展处理器，其将目标设备回放到目标设备。 同样，在主I2C总线上从目标设备绑定到总线主机的数据流被传输到扩展处理器，该处理器回到总线主机。

公开(公告)号：US06516367B1

公开(公告)日：2003-02-04

申请号：US09339707

申请日：1999-06-24

申请人： Michael Anton Barenys ,  Douglas Michael Boecker ,  Joel Gerard Goodwin ,  Paul Nguyen

发明人： Michael Anton Barenys ,  Douglas Michael Boecker ,  Joel Gerard Goodwin ,  Paul Nguyen

IPC分类号： G06F1300

CPC分类号： G06F13/4081

摘要： A method, system and computer program product are provided for detecting the presence of devices, particularly hot plug devices, connected to a bus both during start-up of a computer system and while the system is running. At start-up, and periodically thereafter, all possible device connections are polled by microprocessors, called sub-bus controllers, which include logic for generating a map of components present on each bus. Each map is accessible by the master bus controller. During system run-time, periodic polling, may be continuous thereby providing a real time device status map for every available bus connection.

摘要翻译： 提供了一种方法，系统和计算机程序产品，用于在计算机系统启动期间和系统运行时检测连接到总线的设备，特别是热插拔设备的存在。 在启动时，并且周期性地，所有可能的设备连接被微处理器轮询，称为子总线控制器，其包括用于生成每个总线上存在的组件的映射的逻辑。 每个地图可由主总线控制器访问。 在系统运行期间，定期轮询可以是连续的，从而为每个可用的总线连接提供实时的设备状态图。

公开(公告)号：US06179209B2

公开(公告)日：2001-01-30

申请号：US08974096

申请日：1997-11-19

申请人： Joel Gerard Goodwin ,  Scott Harlan Isensee ,  John Martin Mullaly

发明人： Joel Gerard Goodwin ,  Scott Harlan Isensee ,  John Martin Mullaly

IPC分类号： G06K700

CPC分类号： G06K7/0008 ,  G06K19/077 ,  G06K19/07741 ,  G06K2017/0067

摘要： A data processing system has a reader device adapted to read information residing on a first type of storage article (such as a floppy diskette), and a holder is provided which is substantially identical in size and shape to the first type of storage article, but allows the reader device to read a card which bears machine-readable information, such as a credit card. The holder can have a slot therein for receiving the card, which is aligned within the holder to position a portion of the information medium at an access area of the holder. The machine-readable information can be, for example, encoded on a magnetic strip on the card. The system allows network-based transactions which read from the card as well as write to it.

摘要翻译： 数据处理系统具有适于读取驻留在第一类型的存储物品（例如软盘）上的信息的读取器装置，并且提供了与第一类型的存储物品基本上相同尺寸和形状的保持器，但是 允许阅读器装置读取一张载有机器可读信息的卡，例如信用卡。 保持器可以在其中具有用于接收卡的槽，其在保持器内对准，以将信息介质的一部分定位在保持器的存取区域。 机器可读信息可以例如编码在卡上的磁条上。 该系统允许从卡读取的基于网络的事务以及写入。

公开(公告)号：US6145036A

公开(公告)日：2000-11-07

申请号：US163918

申请日：1998-09-30

申请人： Michael Anton Barenys ,  Curtis Ray Genz ,  Joel Gerard Goodwin ,  Forrest Clifton Gray

发明人： Michael Anton Barenys ,  Curtis Ray Genz ,  Joel Gerard Goodwin ,  Forrest Clifton Gray

IPC分类号： G06F13/42 ,  G06F13/00 ,  G06F11/00

CPC分类号： G06F13/4291

摘要： Polling of devices on an inter-IC (I.sup.2 C) is provided. An expansion processor resides on a primary I.sup.2 C bus. The expansion processor is coupled to a plurality of I.sup.2 C sub-buses each of which may host a plurality of I.sup.2 C devices. Data is transferred between the expansion processor and the plurality of I.sup.2 C devices via the corresponding sub-bus according to an I.sup.2 C protocol. Data transfer is in response to a request initiated by a bus master on the primary I.sup.2 C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which then echos it to the target device. Likewise, a data stream bound from the target device to the bus master on the primary I.sup.2 C bus is transmitted to the expansion processor which then echos it to the bus master. Each of the target devices on the sub-bus can be polled to determine if they have failed. Failure of a device only affects operation of its sub-bus.

摘要翻译： 提供IC（ICI）设备轮询。 扩展处理器驻留在主I2C总线上。 扩展处理器耦合到多个I2C子总线，每个子副总线可以承载多个I2C设备。 根据I2C协议，数据通过相应的副总线在扩展处理器和多个I2C设备之间传输。 数据传输是响应由主I2C总线上的总线主机发起的请求。 总线主机通过寻址扩展处理器与位于其中一个子总线上的目标设备进行通信。 总线主机通过向扩展处理器发送目标设备所在的子总线数目和目标设备的地址来通知目标设备的扩展处理器。 绑定到目标设备的数据流被引导到扩展处理器，然后该扩展处理器回到目标设备。 同样，在主I2C总线上从目标设备绑定到总线主机的数据流被传输到扩展处理器，然后该扩展处理器回到总线主机。 可以轮询子总线上的每个目标设备，以确定它们是否出现故障。 设备故障只影响其子总线的运行。