公开(公告)号：US4942137A

公开(公告)日：1990-07-17

申请号：US393210

申请日：1989-08-14

申请人： Richard D. Sivan ,  James R. Pfiester ,  John E. Leiss

发明人： Richard D. Sivan ,  James R. Pfiester ,  John E. Leiss

IPC分类号： H01L21/308 ,  H01L21/32 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/32 ,  H01L21/3086 ,  H01L21/76235 ,  H01L21/763

摘要： A method for fabricating a self-aligned trench structure in a semiconductor device is disclosed. In accordance with one method for fabricating the trench structure, an oxidation resistant material having an opening is used as a masking layer. The edge of the opening in the masking layer is covered by a sidewall spacer which protects a portion of the substrate from attack by the etchant used to form the trench. The trench is filled with a trench fill material by selective deposition using a seeding material formed on the sidewall of the trench as a nucleation site. After the trench is filled, the sidewall spacer is removed and the underlying substrate is oxidized to form an electrical insulation region around the upper portion of the trench. The mask layer is removed and the remaining substrate is doped using the insulation region surrounding the trench as a dopant mask.

摘要翻译： 公开了一种在半导体器件中制造自对准沟槽结构的方法。 根据制造沟槽结构的一种方法，使用具有开口的抗氧化材料作为掩模层。 掩模层中的开口的边缘由侧壁间隔物覆盖，该侧壁间隔件保护衬底的一部分免受用于形成沟槽的蚀刻剂的侵蚀。 通过使用形成在沟槽的侧壁上的接种材料作为成核位置通过选择性沉积来填充沟槽填充材料。 在填充沟槽之后，去除侧壁间隔物，并且将下面的衬底氧化以在沟槽的上部周围形成电绝缘区域。 去除掩模层，并且使用围绕沟槽的绝缘区域作为掺杂剂掩模来掺杂剩余的衬底。

公开(公告)号：US4545034A

公开(公告)日：1985-10-01

申请号：US505157

申请日：1983-06-17

申请人： Pallab Chatterjee ,  Hisashi Shichijo ,  John E. Leiss

发明人： Pallab Chatterjee ,  Hisashi Shichijo ,  John E. Leiss

IPC分类号： G11C11/401 ,  G11C11/403 ,  G11C14/00 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/788 ,  G11C11/40

CPC分类号： H01L29/7881 ,  G11C11/403

摘要： A transversly injected quasi-floating gate memory cell. A memory transistor in bulk silicon has a channel region in bulk silicon which is capacitatively coupled both to a thin polysilicon quasi-floating gate and to an overlying word line. The thin polysilicon level which comprises the floating gate is not coterminous with the channel region of the memory transistor, but the quasi-floating gate portion of the thin polysilicon layer is connected, through a polysilicon channel region, to a write bit line. The overlying word line thus addresses both the write transistor in a thin polysilicon level and also the memory transistor itself in the substrate.

摘要翻译： 横向注入的准浮动存储单元。 体硅中的存储晶体管具有体硅中的沟道区，其电容耦合到薄多晶硅准浮置栅极和上覆字线。 包括浮置栅极的薄多晶硅层与存储晶体管的沟道区域不相邻，但是薄多晶硅层的准浮置栅极部分通过多晶硅沟道区域连接到写入位线。 因此，叠加字线对于薄多晶硅层中的写入晶体管以及衬底中的存储晶体管本身也是如此。