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公开(公告)号：US4942137A
公开(公告)日：1990-07-17
申请号：US393210
申请日：1989-08-14
IPC分类号： H01L21/308 , H01L21/32 , H01L21/762 , H01L21/763
CPC分类号： H01L21/32 , H01L21/3086 , H01L21/76235 , H01L21/763
摘要： A method for fabricating a self-aligned trench structure in a semiconductor device is disclosed. In accordance with one method for fabricating the trench structure, an oxidation resistant material having an opening is used as a masking layer. The edge of the opening in the masking layer is covered by a sidewall spacer which protects a portion of the substrate from attack by the etchant used to form the trench. The trench is filled with a trench fill material by selective deposition using a seeding material formed on the sidewall of the trench as a nucleation site. After the trench is filled, the sidewall spacer is removed and the underlying substrate is oxidized to form an electrical insulation region around the upper portion of the trench. The mask layer is removed and the remaining substrate is doped using the insulation region surrounding the trench as a dopant mask.
摘要翻译： 公开了一种在半导体器件中制造自对准沟槽结构的方法。 根据制造沟槽结构的一种方法，使用具有开口的抗氧化材料作为掩模层。 掩模层中的开口的边缘由侧壁间隔物覆盖，该侧壁间隔件保护衬底的一部分免受用于形成沟槽的蚀刻剂的侵蚀。 通过使用形成在沟槽的侧壁上的接种材料作为成核位置通过选择性沉积来填充沟槽填充材料。 在填充沟槽之后，去除侧壁间隔物，并且将下面的衬底氧化以在沟槽的上部周围形成电绝缘区域。 去除掩模层，并且使用围绕沟槽的绝缘区域作为掺杂剂掩模来掺杂剩余的衬底。
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公开(公告)号：US5358890A
公开(公告)日：1994-10-25
申请号：US47933
申请日：1993-04-19
IPC分类号： H01L21/32 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76216 , H01L21/32
摘要： A process for forming isolation regions (20) having a self-aligned channel-stop (22) formed by implanting dopant atoms (24) through the isolation regions (22). An isolation mask (15) is formed over an active region (16) in a semiconductor substrate (10). The isolation mask can be constructed from a variety of materials including silicon nitride, silicon oxynitride, boron nitride, polysilicon, and germanium oxide. Thick isolation regions (20) are formed on either side of the isolation mask (15) and an ion implant process is carried out to form doped regions (22) in the substrate (10) immediately below the isolation regions (20). The isolation mask (15) prevents dopant atoms (24) from entering the active region (16) of the substrate (10).
摘要翻译： 一种用于形成具有通过将掺杂剂原子（24）通过隔离区域（22）注入而形成的自对准通道 - 停止（22）的隔离区域（20）的工艺。 隔离掩模（15）形成在半导体衬底（10）中的有源区（16）上。 隔离掩模可以由各种材料构成，包括氮化硅，氮氧化硅，氮化硼，多晶硅和氧化锗。 在隔离掩模（15）的任一侧上形成厚隔离区（20），并且执行离子注入工艺以在隔离区（20）正下方的衬底（10）中形成掺杂区（22）。 隔离掩模（15）防止掺杂剂原子（24）进入衬底（10）的有源区（16）。
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3.发明授权Method of fabricating MOS transistors using selective polysilicon deposition 失效使用选择性聚硅氧烷沉积制造MOS晶体管的方法
公开(公告)号：US5082794A
公开(公告)日：1992-01-21
申请号：US569097
申请日：1990-08-17
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66583 , H01L29/1033 , H01L29/1045 , H01L29/66553 , H01L29/7836 , H01L29/66537 , Y10S148/122
摘要： In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results ina formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.
摘要翻译： 在形成轻掺杂漏极（LDD）晶体管时，首先在有源区上的栅极氧化物上形成薄的多晶硅层。 沉积掩模层并选择性地蚀刻以暴露多晶硅层的中间部分。 该结构可以用作导致形成由一次侧壁间隔物形成的逆T晶体管或常规LDD结构的工艺的一部分。 多晶硅层的暴露的中间部分用于通过选择性多晶硅沉积形成多晶硅栅极。 暴露的中间部分可以被植入用于沟道植入，从而提供对源/漏植入物的自对准。 侧壁间隔件可以形成在暴露部分内部以减小通道长度。 这些侧壁间隔物可以是氮化物以在侧壁间隔物和方便使用的低温氧化物（LTO）掩模之间提供蚀刻选择性。
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公开(公告)号：US4984042A
公开(公告)日：1991-01-08
申请号：US309589
申请日：1989-02-13
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/66553 , H01L29/7836 , H01L29/66537
摘要： In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results in a formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.
摘要翻译： 在形成轻掺杂漏极（LDD）晶体管时，首先在有源区上的栅极氧化物上形成薄的多晶硅层。 沉积掩模层并选择性地蚀刻以暴露多晶硅层的中间部分。 这种结构可以用作导致逆T晶体管或由一次性侧壁间隔物形成的常规LDD结构的过程的一部分。 多晶硅层的暴露的中间部分用于通过选择性多晶硅沉积形成多晶硅栅极。 暴露的中间部分可以被植入用于沟道植入，从而提供对源/漏植入物的自对准。 侧壁间隔件可以形成在暴露部分内部以减小通道长度。 这些侧壁间隔物可以是氮化物以在侧壁间隔物和方便使用的低温氧化物（LTO）掩模之间提供蚀刻选择性。
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公开(公告)号：US4948745A
公开(公告)日：1990-08-14
申请号：US353933
申请日：1989-05-22
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/41783 , H01L29/665 , H01L29/66537 , H01L29/66545
摘要： A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure, with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes. The selectively deposited polycrystalline silicon extends upwardly from the source and drain regions onto the field oxide. The sidewall spacers provide physical and electrical isolation between the gate electrode and the adjacent source and drain electrodes.
摘要翻译： 公开了用于制造升高的源极/漏极IGFET器件的工艺。 根据该方法的一个实施例，提供了硅衬底，其通过场氧化物被分为有源场和场区。 在有源区上形成栅极氧化物，并且在栅极氧化物上沉积多晶硅薄层和氮化硅层。 蚀刻多晶硅和氮化硅以形成堆叠结构，其中间隔物与栅电极的图案中具有与层叠结构基本相同的高度。 在层叠结构的边缘上形成侧壁间隔物，并去除氮化硅。 然后将多晶硅沉积到多晶硅和源极和漏极区域的暴露部分上以完成栅极电极并形成源极和漏极。 选择性沉积的多晶硅从源区和漏区向上延伸到场氧化物上。 侧壁间隔件提供栅电极和相邻的源漏电极之间的物理和电隔离。
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6.发明授权Method for making a self-aligned vertical thin-film transistor in a semiconductor device 失效在半导体器件中制造自对准垂直薄膜晶体管的方法
公开(公告)号：US5229310A
公开(公告)日：1993-07-20
申请号：US887956
申请日：1992-05-26
申请人： Richard D. Sivan
发明人： Richard D. Sivan
IPC分类号： H01L21/336 , H01L27/12 , H01L29/786
CPC分类号： H01L29/6675 , H01L27/12 , H01L29/78642 , Y10S148/15
摘要： A thin-film transistor in a semiconductor device is self-aligned and vertically oriented. In one form of the present invention, the semiconductor device (10) has a vertical wall trench (18) formed in a first dielectric layer (16) and having a predetermined depth. A first current electrode (26) is formed on a bottom surface of the trench while a second current electrode (28) overlies the first dielectric material, each current electrode preferably being formed of polysilicon. A channel region (30) connecting the first and second current electrodes lies along the vertical wall of the trench and has a length substantially equal to the predetermined depth. A control electrode (36) is located within the trench and is also preferably formed of polysilicon. The control electrode is electrically isolated from the first current electrode and the channel region by a second dielectric layer (32).
摘要翻译： 半导体器件中的薄膜晶体管是自对准且垂直取向的。 在本发明的一种形式中，半导体器件（10）具有形成在第一介电层（16）中并具有预定深度的垂直壁沟槽（18）。 第一电流电极（26）形成在沟槽的底表面上，而第二电流电极（28）覆盖在第一介电材料上，每个电流电极优选地由多晶硅形成。 连接第一和第二电流电极的沟道区域（30）沿着沟槽的垂直壁设置，并且具有基本上等于预定深度的长度。 控制电极（36）位于沟槽内，并且还优选地由多晶硅形成。 控制电极通过第二电介质层（32）与第一电流电极和沟道区域电隔离。
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公开(公告)号：US5541132A
公开(公告)日：1996-07-30
申请号：US408653
申请日：1995-03-21
申请人： Robert B. Davies , Vida Ilderem , Mark D. Griswold , Diann Dow , James E. Prendergast , Iksung Lim , Juan Buxo , Richard D. Sivan , James D. Burnett , Frank K. Baker
发明人： Robert B. Davies , Vida Ilderem , Mark D. Griswold , Diann Dow , James E. Prendergast , Iksung Lim , Juan Buxo , Richard D. Sivan , James D. Burnett , Frank K. Baker
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/423 , H01L21/265
CPC分类号： H01L29/66659 , H01L21/823814 , H01L21/823828 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/1045 , H01L29/1083 , H01L29/42368 , Y10S438/981
摘要： An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).
摘要翻译： 具有减小的栅极 - 漏极电容的绝缘栅场效应晶体管（10）和制造场效应晶体管（10）的方法。 掺杂剂阱（13）形成在半导体材料（11）中。 栅极氧化物层（26）形成在掺杂剂阱（13）上，其中栅极氧化物层（26）和具有栅极接触部分（43）和栅极延伸部分（44）的栅极结构（41）。 栅极接触部分（43）允许与栅极结构（41）的电接触，而栅极延伸部分（44）用作有源栅极部分。 与栅极接触部分（43）相邻的栅极氧化物（26）的一部分被加厚以降低场效应晶体管（10）的栅极到漏极电容，从而增加绝缘栅极场效应晶体管（10）的带宽。
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公开(公告)号：US5262352A
公开(公告)日：1993-11-16
申请号：US937025
申请日：1992-08-31
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76834 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L2924/0002
摘要： An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).
摘要翻译： 形成具有衬底（10）的互连结构。 形成在衬底（10）上方的导电层（14）。 形成覆盖导电层（14）的导电层（18）。 通过导电层（18）蚀刻开口（19），暴露导电层（14）的顶部部分，并形成导电层（18）的侧壁。 使用选择性各向同性蚀刻工艺来横向凹入导电层（18）的侧壁。 邻近导电层（18）的侧壁形成侧壁间隔物（22）。 导电层（24）形成在开口（19）内并与隔离物（22）相邻以形成导电层（24和14）之间的互连。 互连是自对准的，并且由于导电层（18）的侧向凹入的侧壁，导电层（18）可靠地与互连隔离。
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公开(公告)号：US5408130A
公开(公告)日：1995-04-18
申请号：US286592
申请日：1994-08-05
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L23/48 , H01L29/46 , H01L29/62
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76834 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L2924/0002
摘要： An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).
摘要翻译： 形成具有衬底（10）的互连结构。 形成在衬底（10）上方的导电层（14）。 形成覆盖导电层（14）的导电层（18）。 通过导电层（18）蚀刻开口（19），暴露导电层（14）的顶部部分，并形成导电层（18）的侧壁。 使用选择性各向同性蚀刻工艺来横向凹入导电层（18）的侧壁。 邻近导电层（18）的侧壁形成侧壁间隔物（22）。 导电层（24）形成在开口（19）内并与隔离物（22）相邻以形成导电层（24和14）之间的互连。 互连是自对准的，并且由于导电层（18）的侧向凹入的侧壁，导电层（18）可靠地与互连隔离。
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公开(公告)号：US5324973A
公开(公告)日：1994-06-28
申请号：US55582
申请日：1993-05-03
申请人： Richard D. Sivan
发明人： Richard D. Sivan
CPC分类号： H01L27/1108 , Y10S257/903
摘要： A semiconductor memory cell (10) includes vertically disposed MOS pass transistors (32, 34) and MOS inverters (12, 14) contained in trench structures in a semiconductor substrate (11). An MOS inverter (12) has a toroidal shared-gate electrode (48) overlying the wall surface of a first trench (36). A pass transistor (32) has a gate electrode (84) in a third trench (40). A first buried drain region (62) resides in the substrate (11) adjacent to the first trench (36), and is located a first distance from the substrate surface. A second buried drain region (64) resides in the substrate (11) adjacent to the second trench (32), and is located a second distance from the substrate surface. The inverter (12) and the pass transistor (32) are electrically coupled by the first and second buried layers (62, 64). The channel length (90) of the driver transistor (16) in the inverter (12) and the pass transistor (32) is determined by the first and second distances, respectively. Accordingly, the cell ratio of the memory cell (10) (ratio of W/L values) is also determined by the differential depth of the first and second buried drain regions (62, 64).
摘要翻译： 半导体存储单元（10）包括在半导体衬底（11）中包含在沟槽结构中的垂直设置的MOS通过晶体管（32,34）和MOS反相器（12,14）。 MOS反相器（12）具有覆盖在第一沟槽（36）的壁表面上的环形共享栅电极（48）。 传输晶体管（32）在第三沟槽（40）中具有栅电极（84）。 第一掩埋漏极区域（62）位于邻近第一沟槽（36）的衬底（11）中，并且位于离衬底表面的第一距离处。 第二埋漏区（64）驻留在与第二沟槽（32）相邻的衬底（11）中，并且位于离衬底表面的第二距离处。 逆变器（12）和通过晶体管（32）通过第一和第二掩埋层（62,64）电耦合。 逆变器（12）中的驱动晶体管（16）和通过晶体管（32）的沟道长度（90）分别由第一和第二距离决定。 因此，存储单元（10）的单元比（W / L值的比））也由第一和第二埋漏区（62,64）的差分深度确定。
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