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公开(公告)号：US06756853B2
公开(公告)日：2004-06-29
申请号：US10167149
申请日：2002-06-11
IPC分类号： H03B2700
CPC分类号： H03K3/0322 , H03K3/011
摘要： An apparatus comprising a plurality of serially coupled delay cells configured to generate an output signal having a frequency varied in response to a control signal. Each of the delay cells may be configured to generate one or more intermediate signals in response to the control signal and present the intermediate signals to a next of the delay cells. One or more next to the last of the intermediate signals may be fed back to a first of the delay cells. One or more last of the intermediate signals may be presented as the output signal.
摘要翻译： 一种包括多个串联的延迟单元的装置，被配置为产生具有响应于控制信号而变化的频率的输出信号。 每个延迟单元可以被配置为响应于控制信号产生一个或多个中间信号，并将中间信号呈现给下一个延迟单元。 一个或多个中间信号的最后一个可以被反馈到第一个延迟单元。 一个或多个中间信号的最后一个可以被呈现为输出信号。
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公开(公告)号：US06621299B1
公开(公告)日：2003-09-16
申请号：US09849640
申请日：2001-05-04
申请人： Todd A. Randazzo , Matthew J. Russell , Kenneth S. Szajda , Jonathan A. Schmitt , Kenneth G. Richardson , Timothy P. McGonagle
发明人： Todd A. Randazzo , Matthew J. Russell , Kenneth S. Szajda , Jonathan A. Schmitt , Kenneth G. Richardson , Timothy P. McGonagle
IPC分类号： H03K1900
CPC分类号： H03K19/003
摘要： An integrated circuit having input output buffers, where the integrated circuit is powered by at least a core power supply and an input output power supply. A level shifter receives an active low signal that indicates that the core power supply has powered down. The level shifter then outputs a known state upon receipt of the active low signal. A control circuit receives the known state form the level shifter, and then tristates the input output buffers upon receipt of the known state.
摘要翻译： 一种具有输入输出缓冲器的集成电路，其中集成电路至少由核心电源和输入输出电源供电。 电平移位器接收到指示核心电源已断电的低电平有效信号。 然后，电平移位器在接收到有效低电平信号时输出已知状态。 控制电路接收电平移位器的已知状态，然后在接收到已知状态时将输入输出缓冲器三态化。
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公开(公告)号：US06181214B2
公开(公告)日：2001-01-30
申请号：US09448677
申请日：1999-11-24
IPC分类号： H02H720
CPC分类号： H03K3/013 , H03K3/0307
摘要： An integrated circuit oscillator input cell has an oscillator input pad, an oscillator feedback pad, a core terminal, an inverter and an electrostatic discharge protection circuit. The inverter has an inverter input, which is coupled to the oscillator input pad, and an inverter output, which is coupled to the oscillator feedback pad and the core terminal. The electrostatic discharge protection circuit includes a plurality of N-channel protection transistors, which are coupled to the oscillator input pad. The N-channel protection transistors are the only protection transistors that are coupled to the oscillator input pad.
摘要翻译： 集成电路振荡器输入单元具有振荡器输入焊盘，振荡器反馈焊盘，核心端子，反相器和静电放电保护电路。 逆变器具有耦合到振荡器输入焊盘的反相器输入和耦合到振荡器反馈板和核心端子的反相器输出。 静电放电保护电路包括耦合到振荡器输入焊盘的多个N沟道保护晶体管。 N沟道保护晶体管是耦合到振荡器输入板的唯一保护晶体管。
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公开(公告)号：US08159894B2
公开(公告)日：2012-04-17
申请号：US12003216
申请日：2007-12-20
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains.
摘要翻译： 一次性可编程存储器。 一次性可编程存储器具有用于读取反熔丝的反熔丝和读取电路。 隔离晶体管将反熔丝耦合到读取电路。 读取电路和隔离晶体管具有不同的功率域。
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公开(公告)号：US20090059645A1
公开(公告)日：2009-03-05
申请号：US12003216
申请日：2007-12-20
CPC分类号： G11C17/18
摘要： A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains.
摘要翻译： 一次性可编程存储器。 一次性可编程存储器具有用于读取反熔丝的反熔丝和读取电路。 隔离晶体管将反熔丝耦合到读取电路。 读取电路和隔离晶体管具有不同的功率域。
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公开(公告)号：US07002419B2
公开(公告)日：2006-02-21
申请号：US10662188
申请日：2003-09-15
IPC分类号： H03L7/08
CPC分类号： G11C29/12015 , G11C7/22 , G11C7/222 , G11C29/028 , G11C29/50012 , H03L7/0893 , H03L7/093
摘要： A phase-locked loop within an integrated circuit assembly is provided. The phase-locked loop includes a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly. One or more metal layers are formed over and interconnect the plurality of semiconductor devices in a metallization pattern. The phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.
摘要翻译： 提供集成电路组件内的锁相环。 锁相环包括在集成电路组件的基极层上以基层图案布置的多个半导体器件子电池。 在金属化图案中形成多个金属层并在多个半导体器件上互连。 锁相环具有随着对金属化图案的改变而可改变的输出频率范围，而基本层图案没有相应的改变。
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7.发明授权公开(公告)号：US06300800B1
公开(公告)日：2001-10-09
申请号：US09448307
申请日：1999-11-24
IPC分类号： H03K19094
CPC分类号： H03K19/018521 , H03K19/09429
摘要： An integrated circuit output buffer includes a core terminal, a pad terminal, a pad pull-up transistor, a pad pull-down transistor, a pull-up voltage protection transistor, and a selectively conductive pad voltage feedback path. The pad pull-up transistor and the pad pull-down transistor are coupled to the pad terminal and are biased to respectively charge and discharge the pad terminal in response to a data signal received on the core terminal. The pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal and a well terminal. The selectively conductive pad voltage feedback path is coupled between the pad terminal and the well terminal of the pull-up voltage protection transistor.
摘要翻译： 集成电路输出缓冲器包括芯端子，焊盘端子，焊盘上拉晶体管，焊盘下拉晶体管，上拉电压保护晶体管和选择性导电焊盘电压反馈路径。 焊盘上拉晶体管和焊盘下拉晶体管耦合到焊盘端子，并且被偏置以分别响应于在核心端子上接收的数据信号对焊盘端子进行充电和放电。 上拉电压保护晶体管串联耦合在焊盘上拉晶体管和焊盘端子之间，并具有控制端子和阱端子。 选择性导电焊盘电压反馈路径耦合在焊盘端子和上拉电压保护晶体管的阱端子之间。
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