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    PROCESSING MEMORY ACCESS INSTRUCTIONS THAT HAVE DUPLICATE MEMORY INDICES
    5.
    发明申请
    PROCESSING MEMORY ACCESS INSTRUCTIONS THAT HAVE DUPLICATE MEMORY INDICES 有权
    处理存储器访问指令，具有重复的存储器指示

    公开(公告)号：US20140095779A1

    公开(公告)日：2014-04-03

    申请号：US13631378

    申请日：2012-09-28

    申请人： Andrew T. Forsyth ,  Dennis R. Bradford ,  Jonathan C. Hall

    发明人： Andrew T. Forsyth ,  Dennis R. Bradford ,  Jonathan C. Hall

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G06F12/00 ,  G06F3/06 ,  G06F3/0608 ,  G06F3/0641 ,  G06F9/30 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F11/1453 ,  G06F12/0246

    摘要： A method of an aspect includes receiving an instruction indicating a first source packed memory indices, a second source packed data operation mask, and a destination storage location. Memory indices of the packed memory indices are compared with one another. One or more sets of duplicate memory indices are identified. Data corresponding to each set of duplicate memory indices is loaded only once. The loaded data corresponding to each set of duplicate memory indices is replicated for each of the duplicate memory indices in the set. A packed data result in the destination storage location in response to the instruction. The packed data result includes data elements from memory locations that are indicated by corresponding memory indices of the packed memory indices when not blocked by corresponding elements of the packed data operation mask.

    摘要翻译： 一方面的方法包括接收指示第一源打包存储器索引的指令，第二源打包数据操作掩码和目的地存储位置。 将打包的内存索引的内存索引彼此进行比较。 识别一组或多组重复的内存索引。 与每组重复存储器索引对应的数据仅加载一次。 对于集合中的每个重复存储器索引，复制对应于每组重复存储器索引的加载数据。 打包数据导致响应于该指令的目的地存储位置。 打包数据结果包括来自存储器位置的数据元素，当不被打包数据操作掩码的相应元素阻塞时，由打包的存储器索引的相应存储器索引指示。

    Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks
    6.
    发明授权
    Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks 有权

    公开(公告)号：US10387151B2

    公开(公告)日：2019-08-20

    申请号：US13250223

    申请日：2011-09-30

    申请人： Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

    发明人： Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

    IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F12/06 ,  G06F12/08 ,  G06F9/345

    摘要： Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

    COALESCING ADJACENT GATHER/SCATTER OPERATIONS
    10.
    发明申请
    COALESCING ADJACENT GATHER/SCATTER OPERATIONS 有权
    加油相机/散热器操作

    公开(公告)号：US20140181464A1

    公开(公告)日：2014-06-26

    申请号：US13997784

    申请日：2012-12-26

    申请人： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

    发明人： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

    IPC分类号： G06F12/10

    CPC分类号： G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

    摘要： According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

    摘要翻译： 根据一个实施例，处理器包括指令解码器，用于解码从存储器收集数据元素的第一指令，所述第一指令具有指定第一存储位置的第一操作数和指定存储多个数据元素的第一存储器地址的第二操作数 。 处理器还包括执行单元，其响应于第一指令而耦合到指令解码器，基于由第二操作数指示的第一存储器地址从存储器位置读取连续的第一和第二数据元素，并且 将所述第一数据元素存储在所述第一存储位置的第一条目中，以及将第二数据元素存储在与所述第一存储位置的所述第一条目相对应的第二存储位置的第二条目中。