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公开(公告)号：US08930678B2
公开(公告)日：2015-01-06
申请号：US13457257
申请日：2012-04-26
IPC分类号： G06F9/30
CPC分类号： G06F9/30152 , G06F9/30036 , G06F9/3017 , G06F9/3808
摘要： Techniques to increase the consumption rate of raw instruction bytes within an instruction fetch unit. An instruction fetch unit according to embodiments of the present invention may include a prefetch buffer, a set of bypass multiplexers, an array of bypass latches, a byte-block multiplexer, an instruction alignment multiplexer, a predecode cache, and an instruction length decoder. Raw instruction bytes may be steered from the bypass latches into macro-instructions for consumption by the instruction length decoder, which may generate micro-instructions from the macro-instructions. Embodiments of the present invention may de-couple a latency for reading raw instruction bytes from the prefetch buffer from consuming raw instruction bytes by the instruction length decoder.
摘要翻译： 增加指令获取单元中原始指令字节的消耗率的技术。 根据本发明的实施例的指令获取单元可以包括预取缓冲器，一组旁路多路复用器，旁路锁存器阵列，字节块多路复用器，指令对准多路复用器，预解码高速缓存和指令长度解码器。 原始指令字节可以从旁路锁存器转移到指令长度解码器消耗的宏指令中，指令长度解码器可以从宏指令生成微指令。 本发明的实施例可以将用于从预取缓冲器读取原始指令字节的延迟与由指令长度解码器消耗原始指令字节取消耦合。
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公开(公告)号：US09710277B2
公开(公告)日：2017-07-18
申请号：US12890574
申请日：2010-09-24
CPC分类号： G06F9/3822 , G06F1/3237 , G06F1/3287 , G06F9/3017 , G06F9/382 , G06F9/3869 , G06F9/3889 , Y02D10/128
摘要： A processor and method are disclosed. In one embodiment the processor includes a prefetch buffer that stores macro instructions. The processor also includes a clock circuit that can provide a clock signal for at least some of the functional units within the processor. The processor additionally includes macro instruction decode logic that can determine a class of each macro instruction. The processor also includes a clock management unit that can cause the clock signal to remain in a steady state entering at least one of the units in the processor that do not operate on a current macro instruction being decoded. Finally, the processor also includes at least one instruction decoder unit that can decode the first macro instruction into one or more opcodes.
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公开(公告)号：US09367317B2
公开(公告)日：2016-06-14
申请号：US13935363
申请日：2013-07-03
CPC分类号： G06F9/30145 , G06F9/325 , G06F9/381 , G06F9/3822
摘要： A processor includes a microcode storage comprising a plurality of microcode flows and a decode logic coupled to the microcode storage. The decode logic is configured to receive a first instruction, decode the first instruction into an entry point vector to a first microcode flow in the microcode storage, the entry point vector comprising a first indicator specifying a number of clock cycles associated with the first microcode flow, initiate the microcode storage, wherein the microcode storage inserts microinstructions of the first microcode flow into an instruction queue, count clock cycles after initiating the microcode storage, and decode a second instruction without first receiving a return from the microcode storage, wherein the second instruction is decoded at a particular clock cycle based on the number of clock cycles associated with the first microcode flow.
摘要翻译： 处理器包括微代码存储器，其包括多个微码流和耦合到微代码存储器的解码逻辑。 解码逻辑被配置为接收第一指令，将第一指令解码为微代码存储器中的第一微代码流的入口点向量，入口点向量包括指定与第一微代码流相关联的时钟周期数量的第一指示符 启动微代码存储，其中微代码存储将第一微代码流的微指令插入到指令队列中，在启动微代码存储之后对计数时钟周期进行解码，并且在不首先从微代码存储器接收到返回的情况下解码第二指令，其中第二指令 基于与第一微码流相关联的时钟周期的数量在特定时钟周期进行解码。
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公开(公告)号：US20120079242A1
公开(公告)日：2012-03-29
申请号：US12890574
申请日：2010-09-24
CPC分类号： G06F9/3822 , G06F1/3237 , G06F1/3287 , G06F9/3017 , G06F9/382 , G06F9/3869 , G06F9/3889 , Y02D10/128
摘要： A processor and method are disclosed. In one embodiment the processor includes a prefetch buffer that stores macro instructions. The processor also includes a clock circuit that can provide a clock signal for at least some of the functional units within the processor. The processor additionally includes macro instruction decode logic that can determine a class of each macro instruction. The processor also includes a clock management unit that can cause the clock signal to remain in a steady state entering at least one of the units in the processor that do not operate on a current macro instruction being decoded. Finally, the processor also includes at least one instruction decoder unit that can decode the first macro instruction into one or more opcodes.
摘要翻译： 公开了一种处理器和方法。 在一个实施例中，处理器包括存储宏指令的预取缓冲器。 该处理器还包括时钟电路，该时钟电路可为处理器内的至少一些功能单元提供时钟信号。 处理器还包括可以确定每个宏指令的类的宏指令解码逻辑。 该处理器还包括一个时钟管理单元，该时钟管理单元可使时钟信号保持在稳定状态，进入处理器中的至少一个不对正在解码的当前宏指令进行操作的单元。 最后，处理器还包括至少一个指令解码器单元，其可以将第一宏指令解码为一个或多个操作码。
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公开(公告)号：US20150012726A1
公开(公告)日：2015-01-08
申请号：US13935363
申请日：2013-07-03
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/325 , G06F9/381 , G06F9/3822
摘要： A processor includes a microcode storage comprising a plurality of microcode flows and a decode logic coupled to the microcode storage. The decode logic is configured to receive a first instruction, decode the first instruction into an entry point vector to a first microcode flow in the microcode storage, the entry point vector comprising a first indicator specifying a number of clock cycles associated with the first microcode flow, initiate the microcode storage, wherein the microcode storage inserts microinstructions of the first microcode flow into an instruction queue, count clock cycles after initiating the microcode storage, and decode a second instruction without first receiving a return from the microcode storage, wherein the second instruction is decoded at a particular clock cycle based on the number of clock cycles associated with the first microcode flow.
摘要翻译： 处理器包括微代码存储器，其包括多个微码流和耦合到微代码存储器的解码逻辑。 解码逻辑被配置为接收第一指令，将第一指令解码为微代码存储器中的第一微代码流的入口点向量，入口点向量包括指定与第一微代码流相关联的时钟周期数量的第一指示符 启动微代码存储，其中微代码存储将第一微代码流的微指令插入到指令队列中，在启动微代码存储之后对计数时钟周期进行解码，并且在不首先从微代码存储器接收到返回的情况下解码第二指令，其中第二指令 基于与第一微码流相关联的时钟周期的数量在特定时钟周期进行解码。
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公开(公告)号：US20130290678A1
公开(公告)日：2013-10-31
申请号：US13457257
申请日：2012-04-26
IPC分类号： G06F9/30
CPC分类号： G06F9/30152 , G06F9/30036 , G06F9/3017 , G06F9/3808
摘要： Techniques to increase the consumption rate of raw instruction bytes within an instruction fetch unit. An instruction fetch unit according to embodiments of the present invention may include a prefetch buffer, a set of bypass multiplexers, an array of bypass latches, a byte-block multiplexer, an instruction alignment multiplexer, a predecode cache, and an instruction length decoder. Raw instruction bytes may be steered from the bypass latches into macro-instructions for consumption by the instruction length decoder, which may generate micro-instructions from the macro-instructions. Embodiments of the present invention may de-couple a latency for reading raw instruction bytes from the prefetch buffer from consuming raw instruction bytes by the instruction length decoder.
摘要翻译： 增加指令获取单元中原始指令字节的消耗率的技术。 根据本发明的实施例的指令获取单元可以包括预取缓冲器，一组旁路多路复用器，旁路锁存器阵列，字节块多路复用器，指令对准多路复用器，预解码高速缓存和指令长度解码器。 原始指令字节可以从旁路锁存器转移到指令长度解码器消耗的宏指令中，指令长度解码器可以从宏指令生成微指令。 本发明的实施例可以将用于从预取缓冲器读取原始指令字节的延迟与由指令长度解码器消耗原始指令字节相关联。
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