公开(公告)号：US20070261059A1

公开(公告)日：2007-11-08

申请号：US11410398

申请日：2006-04-25

申请人： Joseph Orth ,  Erin Handgen ,  Leith Johnson ,  Jonathan Lotz

发明人： Joseph Orth ,  Erin Handgen ,  Leith Johnson ,  Jonathan Lotz

IPC分类号： G06F9/46

CPC分类号： G06F12/0284

摘要： Array based memory abstraction in a multiprocessor computing system is disclosed. A plurality of memory resources are operably connected to an interconnect fabric. In a plurality of memory blocks, each memory block represents a contiguous portion of the plurality of memory resources. A cell is operably connected to the interconnect fabric. The cell has an agent with a fabric abstraction block, and the fabric abstraction block includes a block table having an entry for each of the plurality of memory blocks. A memory controller is associated with the agent, is operably connected to the interconnect fabric, and is configured to control a portion of the plurality of memory blocks.

摘要翻译： 公开了一种在多处理器计算系统中的基于阵列的存储器抽象。 多个存储器资源可操作地连接到互连结构。 在多个存储块中，每个存储块表示多个存储器资源的连续部分。 电池可操作地连接到互连织物。 所述小区具有具有织物抽象块的代理，并且所述结构抽象块包括具有用于所述多个存储器块中的每一个的条目的块表。 存储器控制器与代理相关联，可操作地连接到互连结构，并且被配置为控制多个存储器块的一部分。

公开(公告)号：US5796997A

公开(公告)日：1998-08-18

申请号：US647539

申请日：1996-05-15

申请人： Gregg Lesartre ,  Jonathan Lotz

发明人： Gregg Lesartre ,  Jonathan Lotz

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857

摘要： A fast nullify system and method facilitate handling of nullification dependencies in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are permitted to execute out of order. After execution of an instruction by an execution unit, instructions are retired by a retire mechanism, which transforms the results of instruction execution to the architecture state. While instructions are executed in the reordering mechanism nullifying instructions and dependent instructions that can potentially be nullified by the nullifying instructions are identified. For each dependent instruction, a determination is made as to whether the dependent instruction qualifies for a fast nullify procedure in that the dependent instruction has less operands than a number that can be read by the execution unit. When a dependent instruction qualifies, then the qualified dependent instruction and its corresponding nullifying instruction are permitted to execute substantially concurrently. During execution of the dependent instruction, the execution unit reads a previous result of a target register associated with the dependent instruction. The current result of the dependent instruction is stored in the target register when the dependent instruction is not nullified by the nullifying instruction. In contrast, the previous result is maintained in the target register when the dependent instruction is nullified by the nullifying instruction.

摘要翻译： 快速无效系统和方法便于处理执行无序指令的处理器中的无效依赖关系。 指令从指令获取机制转发到重新排序机制，其中指令被允许执行无序。 在执行单元执行指令之后，指令由退出机制退出，退出机制将指令执行结果转换到架构状态。 虽然在重新排序机制中执行指令，但是识别可能被无效指令潜在地否定的无效指令和依赖指令。 对于每个相关指令，确定依赖指令是否符合快速无效程序，因为从属指令的操作数少于可由执行单元读取的数字。 当依赖指令限定时，允许合格依赖指令及其相应的无效指令基本同时执行。 在执行依赖指令期间，执行单元读取与从属指令相关联的目标寄存器的先前结果。 当依赖指令不被无效指令置为空时，依赖指令的当前结果被存储在目标寄存器中。 相反，当依赖指令被无效指令无效时，先前的结果保持在目标寄存器中。

公开(公告)号：US20050265089A1

公开(公告)日：2005-12-01

申请号：US11074526

申请日：2005-03-07

申请人： Jonathan Lotz ,  Daniel Krueger ,  Manuel Cabanas-Holmen

发明人： Jonathan Lotz ,  Daniel Krueger ,  Manuel Cabanas-Holmen

IPC分类号： H03K19/23 ,  G11C7/00 ,  G11C29/00 ,  H03K3/037

CPC分类号： H03K3/0375

摘要： In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

公开(公告)号：US5901061A

公开(公告)日：1999-05-04

申请号：US653581

申请日：1996-05-24

申请人： Neela Bhakta Gaddis ,  Samuel D. Naffziger ,  Jonathan Lotz

发明人： Neela Bhakta Gaddis ,  Samuel D. Naffziger ,  Jonathan Lotz

IPC分类号： G01R31/30 ,  G06F11/26 ,  G06F17/50

CPC分类号： G06F11/261 ,  G06F17/5022 ,  G01R31/3016

摘要： A method of using a fet level simulator to check for races in a digital design. The method comprises varying digital design models input into the simulator. Each model comprises a clock gater circuit producing clocks with differing overlaps and dead times. Raw data files corresponding to each model input are generated by the fet level simulator. The raw data files preferably comprise lists of node values with corresponding time stamps. Corresponding latch node values in the raw data files are compared to identify the nodes of a circuit which are affected by races. Identifying affected latch nodes allows a race's root cause to be quickly pinpointed. Vector inputs to the fet level simulator may be varied. If vector inputs are varied, comparison of the raw data files comprises comparing the files generated for differing models with common vector inputs. Apparatus for implementing the above method is also disclosed. The method and apparatus provide for increased race coverage, and decrease the time and effort required to debug races once their presence is identified.

摘要翻译： 一种使用胎儿级别模拟器来检查数字设计中的种族的方法。 该方法包括将输入到模拟器中的数字设计模型变化。 每个型号包括产生具有不同重叠和死区时间的时钟门控电路。 对应于每个模型输入的原始数据文件由fet级别模拟器生成。 原始数据文件优选地包括具有相应时间戳的节点值的列表。 比较原始数据文件中相应的锁存节点值，以识别受种族影响的电路节点。 识别受影响的锁存节点允许快速确定种族的根本原因。 可以改变向fet级别模拟器的矢量输入。 如果矢量输入变化，原始数据文件的比较包括将不同模型生成的文件与公共矢量输入进行比较。 还公开了用于实现上述方法的装置。 该方法和装置提供了增加的种族覆盖，并且一旦识别出存在就减少了调试种族所需的时间和精力。

公开(公告)号：US20060050550A1

公开(公告)日：2006-03-09

申请号：US10934035

申请日：2004-09-03

申请人： John Petersen ,  Hassan Naser ,  Jonathan Lotz

发明人： John Petersen ,  Hassan Naser ,  Jonathan Lotz

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

公开(公告)号：US20050251729A1

公开(公告)日：2005-11-10

申请号：US10825398

申请日：2004-04-14

申请人： Jonathan Lotz ,  Daniel Krueger ,  Manuel Cabanas-Holmen

发明人： Jonathan Lotz ,  Daniel Krueger ,  Manuel Cabanas-Holmen

IPC分类号： G06F11/08 ,  G11C7/00 ,  G11C11/417 ,  G11C29/00 ,  H03K3/037 ,  H04J99/00 ,  H04N1/00 ,  H04J15/00

CPC分类号： H03K3/0375

摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.

摘要翻译： 在优选实施例中，本发明提供了一种用于更小和更快的三重冗余锁存器的电路和方法。 三个可设置的存储器元件将相同的逻辑值设置到每个可设置的存储器元件中。 在可设置的存储器元件被设置之后，具有来自第一可设定存储元件，第二存储器元件的输入和对可设置存储器元件的控制的投票结构确定保持在第三可设置存储器元件上的逻辑值。 通过第三可设置存储元件的传播延迟是三重冗余锁存器的唯一传播延迟。

公开(公告)号：US20050168257A1

公开(公告)日：2005-08-04

申请号：US10769337

申请日：2004-01-30

申请人： Manuel Cabanas-Holmen ,  Daniel Krueger ,  Jonathan Lotz

发明人： Manuel Cabanas-Holmen ,  Daniel Krueger ,  Jonathan Lotz

IPC分类号： H03K3/037

CPC分类号： H03K3/0375

摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch with storage node recovery. An input driver is connected to the input of three transfer gates. The output of each transfer gate is connected to a separate output of one of three feedback inverters. The transfer gates are controlled by two control inputs. The inputs of the three feedback inverters are connected the output of the forward inverter/majority voter. The output from each of the three feedback inverters are inputs to the forward inverter/majority voter. The output of the forward inverter/majority voter is connected to the input of the output driver. The output of the output driver is the output of the triple redundant latch.

摘要翻译： 在优选实施例中，本发明提供了一种用于具有存储节点恢复的较小且更快的三重冗余锁存器的电路和方法。 输入驱动器连接到三个传输门的输入端。 每个传输门的输出连接到三个反馈逆变器之一的单独输出。 传输门由两个控制输入控制。 三个反馈逆变器的输入端连接在正向逆变器/多数选择器的输出端。 三个反馈逆变器中的每一个的输出是正向逆变器/多数选择器的输入。 正向逆变器/多数选择器的输出端连接到输出驱动器的输入端。 输出驱动器的输出是三重冗余锁存器的输出。

公开(公告)号：US20060012413A1

公开(公告)日：2006-01-19

申请号：US10894720

申请日：2004-07-19

申请人： John Petersen ,  Hassan Naser ,  Jonathan Lotz

发明人： John Petersen ,  Hassan Naser ,  Jonathan Lotz

IPC分类号： H03K3/037

CPC分类号： H03K3/0375 ,  G11C11/41 ,  G11C29/32 ,  H03K3/012

摘要： In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the second settable memory element, the third settable memory element and control to the settable memory elements determine the logical value held on the first settable memory element. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

公开(公告)号：US20050242828A1

公开(公告)日：2005-11-03

申请号：US10834627

申请日：2004-04-28

申请人： Jonathan Lotz ,  Daniel Krueger ,  Manuel Cabanas-Holmen

发明人： Jonathan Lotz ,  Daniel Krueger ,  Manuel Cabanas-Holmen

IPC分类号： H03K3/037 ,  H03K19/003

CPC分类号： H03K3/0375

摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element set an identical logical value into each settable memory element, and the voting structure/settable memory element. After the settable memory elements, and the voting structure/settable memory element are set, the voting structure/settable memory element with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the voting structure/settable memory element. The propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.

摘要翻译： 在优选实施例中，本发明提供了一种用于更小和更快的三重冗余锁存器的电路和方法。 两个可设置的存储器元件和投票结构/可设置存储元件将相同的逻辑值设置到每个可设置的存储元件中，以及投票结构/可设置存储元件。 在可设置的存储器元件和投票结构/可设置存储元件被设置之后，具有来自第一可设定存储元件，第二存储器元件的输入和对可设置存储器元件的控制的投票结构/可设置存储元件确定保持的逻辑值 在投票结构/可设置的记忆元素上。 通过投票结构/可设置存储元件的传播延迟是三重冗余锁存器的唯一传播延迟。