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公开(公告)号：US20120319886A1
公开(公告)日：2012-12-20
申请号：US13164478
申请日：2011-06-20
摘要： A singled-ended, successive approximation register analog-to-digital converter convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits. The SAR ADC comprises SAR logic, a resistive network, multiple switches, and first and second LSB capacitors. The switches also comprises two sets of switches coupled to the resistive network, each set of switches is configured to couple a selected tap to each of the first and second LSB capacitors. When determining the lower order bits, the SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of both taps changes by a decreasing amount with each succeeding bit being determined.
摘要翻译： 单端逐次逼近寄存器模数转换器将模拟输入电压转换成包括m个高位位和多个低位位的数字表示。 SAR ADC包括SAR逻辑，电阻网络，多个开关以及第一和第二LSB电容。 开关还包括耦合到电阻网络的两组开关，每组开关被配置为将所选择的抽头耦合到第一和第二LSB电容器中的每一个。 当确定低阶位时，SAR逻辑被配置为控制开关组，以将第一和第二抽头从其中一个较低位确定的下一个周期改变为下一个较低阶的下一个周期 确定位，使得两个抽头的电压随着每个后续位被确定而减小量。
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公开(公告)号：US08395538B2
公开(公告)日：2013-03-12
申请号：US13164478
申请日：2011-06-20
IPC分类号： H03M1/34
摘要： A singled-ended, successive approximation register analog-to-digital converter convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits. The SAR ADC comprises SAR logic, a resistive network, multiple switches, and first and second LSB capacitors. The switches also comprises two sets of switches coupled to the resistive network, each set of switches is configured to couple a selected tap to each of the first and second LSB capacitors. When determining the lower order bits, the SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of both taps changes by a decreasing amount with each succeeding bit being determined.
摘要翻译： 单端逐次逼近寄存器模数转换器将模拟输入电压转换成包括m个高位位和多个低位位的数字表示。 SAR ADC包括SAR逻辑，电阻网络，多个开关以及第一和第二LSB电容。 开关还包括耦合到电阻网络的两组开关，每组开关被配置为将所选择的抽头耦合到第一和第二LSB电容器中的每一个。 当确定低阶位时，SAR逻辑被配置为控制开关组，以将第一和第二抽头从其中一个较低位确定的下一个周期改变为下一个较低阶的下一个周期 确定位，使得两个抽头的电压随着每个后续位被确定而减小量。
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3.发明授权Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency 有权自动配置锁相环，自动保持恒定的阻尼因子，并将环路带宽调整到参考频率的恒定比例公开(公告)号：US09401722B2
公开(公告)日：2016-07-26
申请号：US13525285
申请日：2012-06-16
申请人： Ajay kumar , Krishnaswamy Nagaraj , Joonsung Park
发明人： Ajay kumar , Krishnaswamy Nagaraj , Joonsung Park
CPC分类号： H03L7/107 , H03L7/06 , H03L7/087 , H03L7/0896 , H03L7/0898 , H03L7/093 , H03L7/1072 , H03L7/1075 , H03L7/18 , H03L2207/04
摘要： A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.
摘要翻译： 锁相环（PLL）包括被编程为自动产生一组控制信号以选择电荷泵电流并且积分电容值以自动调整PLL的环路带宽的状态机。 电荷泵DAC产生由状态机控制信号控制的电荷泵电流。 积分器集成了电荷泵输出电流，以产生集成的电荷泵输出信号。 积分器具有通过来自状态机的控制信号可切换地选择的多个电容器，以产生积分电容值。 压控振荡器（VCO）响应于集成的电荷泵输出信号产生PLL输出频率。
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4.发明申请公开(公告)号：US20120319786A1
公开(公告)日：2012-12-20
申请号：US13525285
申请日：2012-06-16
申请人： Ajay kumar , Krishnaswamy Nagaraj , Joonsung Park
发明人： Ajay kumar , Krishnaswamy Nagaraj , Joonsung Park
IPC分类号： H03L7/02
CPC分类号： H03L7/107 , H03L7/06 , H03L7/087 , H03L7/0896 , H03L7/0898 , H03L7/093 , H03L7/1072 , H03L7/1075 , H03L7/18 , H03L2207/04
摘要： A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.
摘要翻译： 锁相环（PLL）包括被编程为自动产生一组控制信号以选择电荷泵电流并且积分电容值以自动调整PLL的环路带宽的状态机。 电荷泵DAC产生由状态机控制信号控制的电荷泵电流。 积分器集成了电荷泵输出电流，以产生集成的电荷泵输出信号。 积分器具有通过来自状态机的控制信号可切换地选择的多个电容器，以产生积分电容值。 压控振荡器（VCO）响应于集成的电荷泵输出信号产生PLL输出频率。
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